AMD Xilinx ZCU670 User Manual page 7

• PS GTR (bank 505) assignment
USB3 (1 GTR)
○
FMCP HSPC DP (3 GTR)
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• PL GTY assignment (2 quads, 8 total GTY)
2x2 zSFP+ (4 GTY on bank GTY127)
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FMCP HSPC DP (4 GTY, bank GTY128)
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• PS MIO connectivity
PS MIO[0:5, 7:12]: dual QSPI
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PS MIO[13]: PS_GPIO2
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PS MIO[14:17]: 2 channels of I2C
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PS MIO[18:19]: UART0 (1 of 3 FT4232 UART channels)
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PS MIO[22:23]: PS_PB, PS_LED I/F
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PS MIO[26]: PMU_INPUT
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PS MIO[27:30]: SFP[0:3] TX_DISABLE
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PS MIO[32:37]: PMU_GPO[0:5]
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PS MIO[38]: PS_GPIO1
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PS MIO[39:43, 45:51]: SD I/F
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PS MIO[52:63]: USB3.0
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PS MIO[64:77]: Ethernet RGMII
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• PL I/O connections
PL user GPIO pushbutton
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PL CPU reset pushbutton
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PL user GPIO LEDs (4)
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• Security—PSBATT button battery backup
• SYSMON header
• Operational switches (power on/off, PS_PROG_B, boot mode DIP switch)
• Operational status LEDs (INIT, DONE, PS STATUS, PGOOD)
• Power management
• System controller (MSP430)
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
Chapter 1: Introduction
www.xilinx.com
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