AMD Xilinx ZCU670 User Manual page 35

PMU GPO (MIO 32-37)
The platform management unit (PMU) within the Zynq UltraScale+ RFSoC signals power domain
changes using the PMU output pins for deep-sleep mode. The Zynq UltraScale+ RFSoC PMU
GPO pins are connected to inputs of the MSP430 system controller through the TXS0108E level-
shifter U37. The RFSoC U1 Bank 501 and MSP430 U38 pin numbers are listed in the following
table.
Table 14: XCZU67DR to MSP430 Connections
Net Name
MIO37_PMU_GPO5
MIO36_PMU_GPO4
MIO35_PMU_GPO3
MIO34_PMU_GPO2
MIO33_PMU_GPO1
MIO32_PMU_GPO0
Through the I2C0 bus U1 PS-side MIO[14:15] pins, the PMU has access to the board power
controller PMBus bus (IRPS5401_SDA/SCL) and power monitor PMbus ( INA226_PMBUS_SDA/
SCL). See Figure 8: I2C0 Bus Topology
See the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for details about the PMU
interface.
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU670 board XDC file, referenced in
SDIO (MIO 39-51)
A PS-side interface to an SD card connector is provided for booting and file system storage. This
interface is used for the SD boot mode and supports SD3.0 access post boot.
SD Card Interface
[Figure 2, callout 7]
The ZCU670 board includes a secure digital input/output (SDIO) interface to provide access to
general purpose non-volatile SDIO memory cards and peripherals. Information for the SD I/O
card specification can be found on the
ZCU670 SD card interface supports the SD1_LS configuration boot mode documented in the
Zynq UltraScale+ Device Technical Reference Manual (UG1085).
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
Chapter 3: Board Component Descriptions
MSP430 U38
Pin Name
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
for additional details.
Appendix B: Xilinx Design
SanDisk Corporation or
Constraints.
SD Association websites. The
www.xilinx.com
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