Part 17.2: Expansion Header J2 - Alinx Cyclone IV FPGA User Manual

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39

Part 17.2: Expansion header J2

Figure 17-3 shows the J2 expansion port connection diagram. Pin1, Pin37,
Pin38 are GND, Pin2 is +5V, and Pin39 and Pin40 are +3.3V. In addition to
Pin33 and Pin34, the signals of J2 are connected to the Bank7 of the FPGA in
differential pairs. Users can realize the data communication between LVDS2.5
and LVDS3.3
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Cyclone IV FPGA Development Board AX515 User Manual
P3
P1
P6
R7
N6
N7
N8
GND
VCC3V3
Figure 17-3: Expansion header J2 schematic
Contact Email: rachel.zhou@alinx.com.cn
P2
24
T7
26
N5
28
M5
30
P7
32
M7
34
M8
36
GND
38
VCC3V3
40