Part 8: Ddr2 Dram - Alinx Cyclone IV FPGA User Manual

Figure 7-2: QSPI Flash chip on the FPGA board
Configure chip pin assignments:

Part 8: DDR2 DRAM

The development board contains a high-speed DDR2 DRAM, model:
MT47H64M16HR-3IT, capacity: 1Gbit (64M*16bit), 16bit bus. The FPGA and
DDR2 DRAM on the development board are connected to the IO of BANK3 and
BANK4, and the level is 1.8V. The clock frequency between the FPGA and
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Cyclone IV FPGA Development Board AX515 User Manual
Pin Name
QSPI_CLK
QSPI_CS
QSPI_MISO0
QSPI_MISO1
QSPI_MISO2
QSPI_MISO3
Contact Email: rachel.zhou@alinx.com.cn
FPGA Pin
A7
A6
B7
B6
E9
B8