Part 4.3: Fpga Power Supply - Alinx Cyclone IV FPGA User Manual

signals TCK, TDO, TMS, TDI.
The JTAG interface uses a 10-pin 2.54mm standard connector, and Figure
3-4 shows the JTAG interface on the FPGA development board.
Figure 4-4: JTAG Connector on the FPGA board

Part 4.3: FPGA Power Supply

Next, let's talk about the power supply pin part of the FPGA, where VCCIO
is the power supply pin of the Bank, which determines the level of the IO port
corresponding to each BANK. As shown in Figure 3-5, Bank1, Bank2, Bank5,
Bank6, Bank8 is connected to VCC3V3. The corresponding IO level of these
banks is 3.3V. Bank3 and Bank4 are connected to DDR2. The required IO is
1.8V, so we are connected to VCC1V8. Bank7 we set it to VCCIO7, where we
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Cyclone IV FPGA Development Board AX515 User Manual
Figure 4-3： JTAGE Schematic
Contact Email: rachel.zhou@alinx.com.cn