Part 4.1: Fpga Resources; Part 4.2: Jtag Interface - Alinx Cyclone IV FPGA User Manual

Part 4.1: FPGA Resources

The EP4CE15F23C8 chip contains logic resources, built-in RAM, multiplier,
phase-locked loop, global clock network and IO port. The resources between
different types of FPGAs will be different. The resources of the FPGA model on
the AX515 development board are shown in Figure 3-2 below

Part 4.2: JTAG Interface

First let's talk about the FPGA configuration and debugging interface: JTAG
interface. The function of the JTAG interface is to download the compiled
program (.sof) to the FPGA or download the configuration file (.jic) to the
configuration chip EPCS64. After the sof file is downloaded to the FPGA, it will
be lost after power-off. Re-download it. However, the JIC file that is solidified
into the configuration chip will not be lost after power-off. After power-on, the
FPGA will read the configuration file in the configuration chip EPCS64 and run it.
Figure 3-3 is the schematic part of the JTAG port, which involves the four
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Cyclone IV FPGA Development Board AX515 User Manual
Figure 4-2：FPGA internal resources
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