Part 11: Gigabit Ethernet Interface - Alinx Cyclone IV FPGA User Manual

DS1302 Interface Pin Assignment：

Part 11: Gigabit Ethernet Interface

The AX515 FPGA development board provides network communication
services to users through the Realtek RTL8211EG Ethernet PHY chip. The
RTL8211EG chip supports 10/100/1000 Mbps network transmission rate and
communicates with the FPGA through the GMII interface. RTL8211EG supports
MDI/MDX adaptive, various speed adaptations, Master/Slave adaptation, and
support for MDIO bus for PHY register management.
The RTL8211EG will detect the level status of some specific IOs to
determine their working mode after powered on. Table 11-1 describes the
default setup information after the GPHY chip is powered on.
Configuration Pin
PHYAD[2:0]
SELRGV
AN[1:0]
RX Delay
TX Delay
Mode
When the network is connected to Gigabit Ethernet, the data transmission
of FPGA and PHY chip RTL8211EG is communicated through the GMII bus, the
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Cyclone IV FPGA Development Board AX515 User Manual
Net Name
RTC_SIO
RTC_RESET
RTC_SCLK
Instructions
MDIO/MDC Mode PHY Address
3.3V, 2.5V, 1.5/1.8V voltage
selection
Auto-negotiation configuration
RX clock 2ns delay
TX clock 2ns delay
RGMII or GMII selection
Table 11-1: PHY chip default configuration value
Contact Email: rachel.zhou@alinx.com.cn
FPGA PIN
E6
G9
E5
Configuration value
PHY Address 011
3.3V
(10/100/1000M) adaptive
Delay
Delay
GMII