Alinx Cyclone IV FPGA User Manual page 20

Cyclone IV FPGA Development Board AX515 User Manual
DDR2 is up to 166.7MHz, and the data frequency is up to 333MHz. The
hardware design of DDR2 requires strict consideration of signal integrity. In the
circuit design and PCB design, the matching resistor/terminal resistor, trace
impedance control, and trace length control have been fully considered to
ensure the high-speed stability of DDR2.
Figure 8-1: DDR2 DRAM Schematic
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