Alinx Cyclone IV FPGA User Manual page 28

Gigabit Ethernet pin assignments are as follows：
Signal Name
E_GCLK
E_TXD0
E_TXD1
E_TXD2
E_TXD3
E_TXD4
E_TXD5
E_TXD6
E_TXD7
E_TXEN
E_TXER
E_TXC
E_RXC
E_RXDV
E_RXER
E_RXD0
E_RXD1
E_RXD2
E_RXD3
E_RXD4
E_RXD5
E_RXD6
E_RXD7
E_COL
E_CRS
E_RESET
E_MDC
E_MDIO
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Cyclone IV FPGA Development Board AX515 User Manual
FPGA Pin
H1
F2
E1
G4
J1
H5
J3
K7
J7
G3
L6
J4
E3
J6
B2
H6
G5
H7
E4
D2
C1
C2
B1
H2
J2
F1
K8
L8
Contact Email: rachel.zhou@alinx.com.cn
Description
Ethernet GMII transmit clock
Ethernet Transmit Data bit0
Ethernet Transmit Data bit1
Ethernet Transmit Data bit2
Ethernet Transmit Data bit3
Ethernet Transmit Data bit4
Ethernet Transmit Data bit5
Ethernet Transmit Data bit6
Ethernet Transmit Data bit7
Ethernet transmit enable signal
Ethernet transmit error signal
Ethernet MII transmit clock
Ethernet GMII receive clock
Ethernet receive data valid signal
Ethernet receiving data error
Ethernet Receive Data Bit0
Ethernet Receive Data Bit1
Ethernet Receive Data Bit2
Ethernet Receive Data Bit3
Ethernet Receive Data Bit4
Ethernet Receive Data Bit5
Ethernet Receive Data Bit6
Ethernet Receive Data Bit7
Collision Signal
Carrier Sense Signal
Ethernet Reset Signal
Ethernet Management Clock
Ethernet Management Data