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4 Programming Reference
MSS Bit
MSS is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service
Request Enable register. MSS is set whenever the instrument has one or more reasons for requesting
service. *STB? reads the bits in the Status Byte register but does not clear them.
Error and Output Queues
The Error Queue is a first-in, first-out (FIFO) data register that stores numerical and textual description
of an error or event. Error messages are stored until they are read with
SYSTem:ERRor?
If the queue
overflows, the last error/event in the queue is replaced with error -350,"Queue overflow".
The Output Queue is a first-in, first-out (FIFO) data register that stores instrument-to-controller
messages until the controller reads them. Whenever the queue holds messages, it sets the MAV bit
(4) of the Status Byte register.
Keysight BT2152A/B Operating and Service Guide
101
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