Part 3.2: Gigabit Ethernet Interface - Alinx ZYNQ7000 FPGA User Manual

Part 3.2: Gigabit Ethernet interface

The AX7015 has two Gigabit Ethernet interfaces on the expansion board, one
of which is the connected PS system side. Another Ethernet interface is connected
to the logical IO port of the PL. The Gigabit Ethernet interface connected to the PL
side, needs to be mounted to ZYNQ's AXI bus system by call IP program
The Ethernet chip uses Micrel's KSZ9031RNX Ethernet PHY chip to provide
network communication services to users. The Ethernet PHY chip on the PS side
is connected to the GPIO interface of the PSNK501 of the PS side of ZYNQ. The
Ethernet PHY chip on the PL side is connected to the IO of BANK33. The
KSZ9031RNX chip supports 10/100/1000 Mbps network transmission rate, and
data communication with the MAC layer of the Zynq7000 system through the
RGMII interface. KSZ9031RNX supports MDI/MDX adaptation, various speed
adaptive, Master/Slave adaptation, MDIO bus for PHY register management.
After power-on, the KSZ9031RNX detects the level status of some specific IOs
to determine their working mode. Table 3-2-1 describes the default settings after
the GPHY chip is powered on.
Configuration Pin
PHYAD[2:0]
CLK125_EN
LED_MODE
MODE0~MODE3
When the network is connected to Gigabit Ethernet, the data transmission of
ZYNQ and PHY chip KSZ9031RNX is communicated through the RGMII bus, the
transmission clock is 125Mhz, and the data is sampled on the rising edge and
falling samples of the clock. Figure 3-2-1 and Figure 3-2-2 detailed the connection
of the ZYNQ chip end Ethernet PHY chip:
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ZYNQ FPGA Development Platform AX7015 User Manual
Instructions
MDIO/MDC Mode PHY Address
Enable 125Mhz clock output
selection
LED light mode configuration
Link adaptation and full duplex
configuration
Table 3-2-1: Default setting after power-on of the KS GPHY chip
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Configuration value
PHY Address 011
Enable
Single LED light mode
10/100/1000 adaptive,
compatible with full-duplex,
half-duplex