Part 2.4: Qspi Flash - Alinx ZYNQ7000 FPGA User Manual

DDR3_WE
DDR3_ODT
DDR3_RESET
DDR3_CLK0_P
DDR3_CLK0_N
DDR3_CKE

Part 2.4: QSPI Flash

The core board is equipped with a 256MBit Quad-SPI FLASH chip, model
W25Q256FVEI, which uses the 3.3V CMOS voltage standard. Due to the non-
volatile nature of QSPI FLASH, it can be used as a boot device for the system to
store the boot image of the system. These images mainly include FPGA bit files,
ARM application code, and other user data files. The specific models and related
parameters of QSPI FLASH are shown in Table 2-4-1.
Position
U7
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS section
of the ZYNQ chip. In the system design, the GPIO port functions of these PS ports
need to be configured as the QSPI FLASH interface. Figure 2-4-1 shows the QSPI
Flash in the schematic.
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ZYNQ FPGA Development Platform AX7015 User Manual
PS_DDR_WE_B_502
PS_DDR_ODT_502
PS_DDR_DRST_B_502
PS_DDR_CKP_502
PS_DDR_CKN_502
PS_DDR_CKE_502
Table 2-3-2: DDR3 DRAM Pin Assignment
Model
W25Q256FVEI
Table 2-4-1: QSPI FLASH Specification
U1
ZYNQ
BANK
500
Figure 2-4-1: QSPI Flash in the schematic
Amazon Store: https://www.amazon.com/alinx
Capacity
32M Byte
QSPI_CS
QSPI_SCK
QSPI_D0~QSPI_D3
R19
P18
F20
N19
N18
T19
Factory
Winbond
U7
QSPI FLASH
(W25Q256F)