Alinx KINTEX-7 FPGA User Manual page 36

GTX transceiver TX of FPGA BANK118 to realize high-speed SDI video output.
The hardware connection diagram of GV8500 chip and FPGA is shown in
Figure 3-4-1:
The pin assignment of the 1
Signal Name
SDI1_3G_TXN
SDI1_3G_TXP
SDI1_SD_HD
The pin assignment of the 2
Signal Name
SDI2_3G_TXN
SDI2_3G_TXP
SDI2_SD_HD
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KINTEX-7 FPGA Development Board AV7K300 User Manual
Figure 3-4-1: SDI Output Interface Schematic
SDI output:
st
FPGA Pin
BANK118_TX0_N
BANK118_TX0_P
B18_L3_N
SDI output:
nd
FPGA Pin
BANK118_TX1_N
BANK118_TX1_P
B18_L3_P
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Pin Number
D1 SDI Output Differential Signal Negative
D2 SDI Output Differential Signal Positive
L13
Pin
Number
C3 SDI Output Differential Signal Negative
C4 SDI Output Differential Signal Positive
L12
Description
SDI Conversion Rate Control
Description
SDI Conversion Rate Control