Part 2.5.2: Gtx Reference Clock - Alinx KINTEX-7 FPGA User Manual

Figure 2-5-2: 200Mhz System Clock Source Schematic
System Clock pin assignments:

Part 2.5.2: GTX Reference Clock

The AC7K325 core board provides a 125Mhz reference clock for the GTX
transceiver. The reference clock is connected to the reference clock input
REFCLK1P/REFCLK1N of BANK117. The schematic of this clock source is
shown in Figure 2-5-3
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KINTEX-7 FPGA Development Board AV7K300 User Manual
Signal Name
SYS_CLK_P
SYS_CLK_N
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FPGA Pin
AE10
AF10