PCIE_RX5_P
PCIE_RX5_N
PCIE_RX6_P
PCIE_RX6_N
PCIE_RX7_P
PCIE_RX7_N
PCIE_TX0_P
PCIE_TX0_N
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX2_P
PCIE_TX2_N
PCIE_TX3_P
PCIE_TX3_N
PCIE_TX4_P
PCIE_TX4_N
PCIE_TX5_P
PCIE_TX5_N
PCIE_TX6_P
PCIE_TX6_N
PCIE_TX7_P
PCIE_TX7_N
PCIE_CLK_P
PCIE_CLK_N
PCIE_PERST
Part 3.4: SDI Output Interface
There are 2 SDI output interfaces on the carrier board, used GV8500 SDI
driver chips, which supports different formats of data output HDcctv 1.0,
HD-SDI (ST 292), 3G_SDI (ST-424) and SD_SDI (ST259).
The SDI input signal of the GV8500 chip is directly connected with the
35 / 45
KINTEX-7 FPGA Development Board AV7K300 User Manual
BANK115_RX2_P
BANK115_RX2_N
BANK115_RX1_P
BANK115_RX1_N
BANK115_RX0_P
BANK115_RX0_N
BANK116_TX3_P
BANK116_TX3_N
BANK116_TX2_P
BANK116_TX2_N
BANK116_TX1_P
BANK116_TX1_N
BANK116_TX0_P
BANK116_TX0_N
BANK115_TX3_P
BANK115_TX3_N
BANK115_TX2_P
BANK115_TX2_N
BANK115_TX1_P
BANK115_TX1_N
BANK115_TX0_P
BANK115_TX0_N
BANK115_CLK0_P
BANK115_CLK0_N
B12_L16_N
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W4
PCIE Channel 5 Data Receive Positive
W3
PCIE Channel 5 Data Receive Negative
Y6
PCIE Channel 6 Data Receive Positive
Y5
PCIE Channel 6 Data Receive Negative
AA4
PCIE Channel 7 Data Receive Positive
AA3
PCIE Channel 7 Data Receive Negative
L4
PCIE Channel 0 Data Receive Positive
L3
PCIE Channel 0 Data Receive Negative
M2
PCIE Channel 1 Data Receive Positive
M1
PCIE Channel 1 Data Receive Negative
N4
PCIE Channel 2 Data Receive Positive
N3
PCIE Channel 2 Data Receive Negative
P2
PCIE Channel 3 Data Receive Positive
P1
PCIE Channel 3 Data Receive Negative
T2
PCIE Channel 4 Data Receive Positive
T1
PCIE Channel 4 Data Receive Negative
U4
PCIE Channel 5 Data Receive Positive
U3
PCIE Channel 5 Data Receive Negative
V2
PCIE Channel 6 Data Receive Positive
V1
PCIE Channel 6 Data Receive Negative
Y2
PCIE Channel 7 Data Receive Positive
Y1
PCIE Channel 7 Data Receive Negative
R8
PCIE channel reference clock Positive
R7
PCIE channel reference clock Negative
AF25
The reset signal of the PCIE board
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