Alinx KINTEX-7 FPGA User Manual page 15

configuration Bin files and other user data files in use. The specific models and
related parameters of QSPI FLASH are shown in Table 2-4-1.
Position
U14
QSPI FLASH is connected to the dedicated pins of BANK0 and BANK14 of
the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data
and chip select signals are connected to D00~D03 and FCS pins of BANK14
respectively. Figure 2-4-1 shows the hardware connection of QSPI Flash.
QSPI Flash pin assignments:
Signal Name
FPGA_CCLK
FLASH_CE_B
FLASH_D0
FLASH_D1
FLASH_D2
FLASH_D3
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KINTEX-7 FPGA Development Board AV7K300 User Manual
Model
N25Q128
Table 2-4-1: QSPI FLASH Specification
Figure 2-4-1: QSPI Flash Schematic
IO_L6P_T0_FCS_B_14
IO_L1P_T0_D00_MOSI_14
IO_L1N_T0_D01_DIN_14
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Capacity
128M Bit
FPGA Pin Name
CCLK_0
IO_L2P_T0_D02_14
IO_L2N_T0_D03_14
Factory
Numonyx
FPGA Pin Number
B10
U19
P24
R25
R20
R21