Alinx KINTEX-7 FPGA User Manual page 23

J29 connector pin assignment
J29 Pin Signal Name
1 BANK115_TX0_N
3 BANK115_TX0_P
5
7 BANK115_TX1_N
9 BANK115_TX1_P
11
13 BANK115_TX2_N
15 BANK115_TX2_P
17
19 BANK115_TX3_N
21 BANK115_TX3_P
23
25 BANK115_CLK0_N
27 BANK115_CLK0_P
29
31 BANK116_TX0_N
33 BANK116_TX0_P
35
37 BANK116_TX1_N
39 BANK116_TX1_P
41
43 BANK116_TX2_N
45 BANK116_TX2_P
47
49 BANK116_TX3_N
51 BANK116_TX3_P
53
55 BANK116_CLK0_N
57 BANK116_CLK0_P
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KINTEX-7 FPGA Development Board AV7K300 User Manual
FPGA Pin
Y1
Y2
GND -
V1
V2
GND -
U3
U4
GND -
T1
T2
GND -
R7
R8
GND -
P1
P2
GND -
N3
N4
GND -
M1
M2
GND -
L3
L4
GND -
L7
L8
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J29 Pin Signal Name
2 BANK115_RX0_N
4 BANK115_RX0_P
6 GND
8 BANK115_RX1_N
10 BANK115_RX1_P
12 GND
14 BANK115_RX2_N
16 BANK115_RX2_P
18 GND
20 BANK115_RX3_N
22 BANK115_RX3_P
24 GND
26 BANK115_CLK1_N
28 BANK115_CLK1_N
30 GND
32 BANK116_RX0_N
34 BANK116_RX0_P
36 GND
38 BANK116_RX1_N
40 BANK116_RX1_P
42 GND
44 BANK116_RX2_N
46 BANK116_RX2_P
48 GND
50 BANK116_RX3_N
52 BANK116_RX3_P
54 GND
56 BANK116_CLK1_N
58 BANK116_CLK1_P
FPGA Pin
AA3
AA4
-
Y5
Y6
-
W3
W4
-
V5
V6
-
U7
U8
-
T5
T6
-
R3
R4
-
P5
P6
-
M5
M6
-
N7
N8