Part 2.5: Clock Configuration; Part 2.5.1: 200Mhz System Clock Source - Alinx KINTEX-7 FPGA User Manual

Part 2.5: Clock configuration

The core board provides 200Mhz and 125Mhz differential active clocks for
the FPGA system. Provide differential clock sources for FPGA logic part and
high-speed transceiver GTX part respectively. The schematic diagram of the
clock circuit design is shown in Figure 2-5-1:

Part 2.5.1: 200Mhz system clock source

The FPGA core board provides a differential 200MHz FPGA system clock
source for the reference clock of the DDR3 controller. The crystal oscillator
output is connected to the global clock (MRCC) of FPGA BANK33. This global
clock can be used to drive the DDR3 controller and user logic circuits in the
FPGA. The schematic diagram of this clock source is shown in Figure 2-5-2
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KINTEX-7 FPGA Development Board AV7K300 User Manual
Figure 2-5-1: Clock Source in the Core Board
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