Getac 9270D Service Manual page 99

4.4 PCI Interface Signals –Table 4
Name
STOP#
PAR
Type
Stop: STOP# indicates that the Ibex Peak, as a target, is
requesting the initiator to stop the current transaction. STOP#
I/O causes the Ibex Peak, as an initiator, to stop the current
transaction. STOP# is an output when the Ibex Peak is a target
and an input when the Ibex Peak is an initiator.
Calculated/Checked Parity: PAR uses "even" parity
calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. "Even"
parity means that the Ibex Peak counts the number of ones
within the 36 bits plus PAR and the sum is always even. The
Ibex Peak always calculates PAR on 36 bits regardless of the
valid byte enables. The Ibex Peak generates PAR for address
and data phases and only guarantees PAR to be valid one PCI
clock after the corresponding address or data phase. The Ibex
Peak drives and tri-states PAR identically to the AD[31:0]
I/O lines except that the Ibex Peak delays PAR by exactly one
PCI clock. PAR is an output during the address phase
(delayed one clock) for all Ibex Peak initiated transactions.
PAR is an output during the data phase (delayed one clock)
when the Ibex Peak is the initiator of a PCI write transaction,
and when it is the target of a read transaction. Ibex Peak
checks parity when it is the target of a PCI write transaction.
If a parity error is detected, the Ibex Peak will set the
appropriate internal status bits, and has the option to generate
an NMI# or SMI#.
Description