Getac 9270D Service Manual page 133

4.22 LVDS Interface Signals –Table 2
Name
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DAT
A
L_VDD_EN
L_BKLTEN
L_BKLTCTL
Type
I/O EDID support for flat panel display
Control signal (clock) for external SSC clock chip control –
I/O
optional
Control signal (data) for external SSC clock chip control –
I/O
optional
LVDS Panel Power Enable: Panel power control enable
control for LVDS.
I/O
This signal is also called VDD_DBL in the CPIS specification
and is used to control the VDC source to the panel logic.
LVDS Backlight Enable: Panel backlight enable control for
LVDS.
I/O
This signal is also called ENA_BL in the CPIS specification
and is used to gate power into the backlight circuitry.
Panel Backlight Brightness Control: Panel brightness
control for LVDS.
I/O
This signal is also called VARY_BL in the CPIS specification
and is used as the PWM Clock input signal.
Description