Getac 9270D Service Manual page 128

4.21 Clock Interface Signals –Table 1
Name
CLKIN_BCLK_P,
CLKIN_BCLK_N
CLKOUT_BCLK0_P
/
CLKOUT_PCIE8_P,
CLKOUT_BCLK0_N
/ CLKOUT_PCIE8_N
CLKOUT_DP_P /
CLKOUT_BCLK1_P,
CLKOUT_DP_N /
CLKOUT_BCLK1_N
CLKIN_DMI_P,
CLKIN_DMI_N
CLKOUT_DMI_P,
CLKOUT_DMI_N
CLKIN_SATA_P /
CKSSCD_P,
CLKIN_SATA_N /
CKSSCD_N
Type
133 MHz differential reference clock from a clock chip in
I Buffer-Through Mode. Unused when Integrated Clock
Generation is enabled.
133MHz Differential output to Processor or 100 MHz PCIe*
O Gen 1.1 specification differential output to PCI Express
devices.
120 MHz Differential output for DisplayPort reference or
O
133MHz Differential output to Processor
100 MHz differential reference clock from a clock chip in
Buffer-Through Mode.
I Note: This input clock is required to be PCIe 2.0 jitter spec
compliant from a clock chip, for PCIe 2.0 discrete Graphics
platforms.
100MHz Gen2 specification jitter tolerant differential output to
O
processor.
100MHz differential reference clock from a clock chip,
I provided separately from CLKIN_DMI, for use only as a
100MHz source for SATA.
Description