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70D N/B Maintenance 70D N/B Maintenance SERVICE MANUAL FOR SERVICE MANUAL FOR SERVICE MANUAL FOR 9270D 9270D 9270D BY: Wenrong.pu Technical Maintenance Department/GTK MTC Jan. 2010/R01...
1. Hardware Engineering Specification 1.1 Introduction The 9270D motherboard implements Intel’s Calpella platform with Arrandale mobile processor. Arrandale is the next generation of 64-bit, multi-core mobile processors built on 32-nanometer process technology. Throughout this document, Arrandale may be referredto as simply the processor. Based on the low-power/high-performance Nehalem microarchitecture, the processor is designed for a two-chip platform as opposed to the traditional three- chip platforms (processor, GMCH, and ICH).
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Integrated Serial ATA host controllers with independent DMA operation on up to six ports. FIS-based Port Multiplier support on SATA Ports 4 and 5 in AHCI/RAID mode. USB host interface with support for up to fourteen USB ports; two EHCI high-speed USB 2.0 Host controllers, 2 rate matching hubs, seven UHCI host controllers;...
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Intel® Quiet System Technology (Desktop only) Intel® Anti-Theft Technology User expendable peripheral interface built on 9270D system are 3 USB + 1 combo E-SATA ports. 9270D system provides a New Card / Express Card and Mini PCI-E Card. User interface includes internal keyboard, touch pad.
1.2 System Hardware Parts-1 Basic Function Spec Remark Type Intel Arrandale CPU 45/35W (Processor/chipset SOC) Display 18.4 SWXGA + Glare/Non Glare 1680x945 HD+ -Max Brightness :TBD 1920x1080 FHD Chipset Ibex Peak Chipset Memory 0 MB on board Type DDRIII SO-DIMM 1066/1333 MHz Slot 2 SO-DIMM Max Size...
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1.2 System Hardware Parts-2 Spec Basic Function Remark Express Card Slot Type Express 54 x1 USB & PCI-E Function Wake on ring support To be able to disable by BIOS Card Reader 4 in 1 Card Reader Slot Type MS / MS PRO / SD / MMC Access LED Function SDHC Support...
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1.2.1 Intel Arrandale CPU Processor 1.2.1.1 CPU – Intel Arrandale Arrandale Processor Introduction Arrandale is the next generation of 64-bit, multi-core mobile processor built on 32- nanometer process technology. Throughout this document, Auburndale may be referred to as simply the processor. Based on the low-power/high-performance Nehalem micro-architecture, the processor is designed for a two-chip platform as opposed to the traditional three-chip platforms (processor, GMCH, and ICH).
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Up to 8-MB shared instruction/data last-level cache (L3), shared among all cores Intel® Virtualization Technology (Intel® VT-x) Intel® Virtualization Technology for Directed I/O (Intel® VT-d) Intel® Trusted Execution Technology (Intel® TXT) Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1) Supplemental Streaming SIMD Extensions 4.2 (Intel® SSE4.2) Intel®...
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1.2.1.2 Mobile Intel Arrandale system memory support The Integrated Memory Controller (IMC) supports DDR3 protocols with two, independent, 64-bit wide channels each accessing one SO-DIMM. It supports a maximum of one, unbuffered non-ECC DDR3 SO-DIMM per- channel thus allowing up to two device ranks per-channel. DDR3 Data Transfer Rates: — 800 MT/s (PC3-6400), and 1066 MT/s (PC3-8500) DDR3 SO-DIMM Modules: —...
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System Memory Timing Support The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface: tCL = CAS Latency tRCD = Activate Command to READ or WRITE Command delay tRP = PRECHARGE Command Period CWL = CAS Write Latency Command Signal modes = 1n indicates a new command may be issued every clock and 2n indicates a new...
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1.2.2 Intel Platform control HUB Ibex Peak chipset 1.2.2.1 Introduction Direct Media Interface —10 Gb/s each direction, full duplex —Transparent to software PCI Express* —NEW: 8 PCI Express root ports —NEW: PCI Express 2.0 specification running at 2.5GT/s. —NEW: Ports 1-4 and 5-8 can independently be configured to support eight x1s, two x4s, two x2s and four x1s, or one x4 and four x1 port widths.
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PCI Bus Interface —Supports PCI Rev 2.3 Specification at 33 MHz —Four available PCI REQ/GNT pairs —Support for 64-bit addressing on PCI using DAC protocol Integrated Serial ATA Host Controller —Up to six SATA ports —Data transfer rates up to 3.0 Gb/s (300 MB/s). —Integrated AHCI controller External SATA support —NEW: Port Disable Capability...
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—Supports variable length stream slots —Supports multichannel, 32-bit sample depth, 192 kHz sample rate output —Provides mic array support —Allows for non-48 kHz sampling output —Support for ACPI Device USB 2.0 —NEW: Two USB 2.0 Rate Matching Hubs to replace functionality of UHCI controllers —Two EHCI Host Controllers, supporting up to fourteen external ports —Per-Port-Disable Capability —Includes up to two USB 2.0 High-speed Debug Ports...
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Integrated Gigabit LAN Controller —NEW: PCI Express* connection —Integrated ASF Management Controller —Network security with System Defense —Supports IEEE 802.3 —10/100/1000 Mbps Ethernet Support —Jumbo Frame Support Power Management Logic —Supports ACPI 3.0b —ACPI-defined power states (processor driven C states) —ACPI Power Management Timer —SMI# generation —All registers readable/restorable for proper resume from 0 V suspend states...
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Enhanced DMA Controller —Two cascaded 8237 DMA controllers —Supports LPC DMA SMBus —Faster speed, up to 100 kbps —Flexible SMBus/SMLink architecture to optimize for ASF —Provides independent manageability bus through SMLink interface —Supports SMBus 2.0 Specification —Host interface allows processor to communicate via SMBus —Slave interface allows an internal or external Microcontroller to access system resources —Compatible with most two-wire components that are also I2C compatible High Precision Event Timers...
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Real-Time Clock —256-byte battery-backed CMOS RAM —Integrated oscillator components —Lower Power DC/DC Converter implementation Serial Peripheral Interface (SPI) —Supports up to two SPI devices —Supports 20 MHz, 33 MHz SPI devices —Support up to two different erase granularities Interrupt Controller —Supports up to eight PCI interrupt pins —Supports PCI 2.3 Message Signaled Interrupts —Two cascaded 82C59 with 15 interrupts...
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Firmware Hub I/F supports BIOS Memory size up to 8 MBytes Low Pin Count (LPC) I/F —Supports two Master/DMA devices. —Support for Security Device (Trusted Platform Module) connected to LPC. Package —27 mm x 27 mm FCBGA (Desktop Only) —27 mm x 25 mm FCBGA (Mobile Only) —22 mm x 20 mm FCBGA (Mobile SFF Only) Analog Display Port Digital Display...
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1.2.2.2 Features and Functions Digital Media Interface (DMI) Digital Media Interface (DMI) is the chip-to-chip connection between the processor and Ibex Peak chipset. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally.
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PCI Interface The Ibex Peak PCI interface provides a 33 MHz, Revision 2.3 implementation. The Ibex Peak integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal Ibex Peak requests. This allows for combinations of up to four PCI down devices and PCI slots.
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Note: UHCI’s are for debug purposes only and not a production feature. The Ibex Peak supports up to fourteen USB 2.0 ports. All fourteen ports are highspeed, full-speed, and low-speed capable. Ibex Peak’s port-routing logic determines whether a USB port is controlled by one of the UHCI or EHCI controllers.
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read and write accesses. This prevents unauthorized reading of passwords or other system security information. The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just24 hours in advance. Intel®...
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ATI M96 series 1.2.3 GDDR3 1Gb (64Mx16) – K4W1G1646E VDD/VDDQ= 1.5V ± 0.075V at 1066/1333/1600/1800/2000 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin 900MHz fCK for 1800Mb/sec/pin,1000MHz fCK for 2000Mb/sec/pin 8 Banks Posted CAS Programmable CAS Latency(posted CAS): 7,9,11,12,13 Programmable Additive Latency: 0, CL-2 or CL-1 clock Programmable CAS Write Latency: (CWL) =6 (1066Mbps), 7(1333Mbps), 8(1600Mbps), 9(1800Mbps),10(2000Mbps)
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• Average Refresh Period: 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C • Asynchronous Reset • Package : 96 balls FBGA - x16 • All of Lead-Free products are compliant for RoHS • All of products are Halogen-Freetr 1.2.4 Realtek ALC633 High Definition Audio System The ALC663 is a 5.1 Channel High Definition Audio Codec designed for Windows system.
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Multiple analog IO (except MONO, PCBEEP and HP-OUT) are input and output capable with headphone amplifiers. Four linear headphone amplifiers are integrated to drive earphones on port-A, port-D, port-E and port-F. The fifth headphone amplifier on port-I (HPOUT) is designed to drive earphone without external DC blocking capacitors, reducing pop noise caused by the DC blocking capacitors.
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1.2.5 APA2031 Audio Amplifier and APA3010 subwoofer APA2031 APA2030/1 is a monolithic integrated circuit, which provides internal gain control, and a stereo bridged audio power amplifiers capable of producing 2.6W (1.9W) into 3Ω with less than 10% (1.0%) THD+N. By control the two gain setting pins, Gain0 and Gain1, The amplifier can provide 6dB, 10dB, 15.6dB, and 21.6dB gain settings.
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Low Distortion –2.5W, at VDD=5V, BTL, RL=3W THD+N=0.1% –2.1W, at VDD=5V, BTL, RL=4W THD+N=0.1% Output Power at 1% THD+N –2.6W, at VDD=5V, BTL, RL=3W –2.3W, at VDD=5V, BTL, RL=4W at 10% THD+N –3.3W at VDD=5V, BTL, RL=3W –2.7W at VDD=5V, BTL, RL=4W Depop Circuitry Integrated Thermal shutdown protection and over current protection circuitry...
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High supply voltage ripple rejection Surface-Mount Packaging –MSOP-8-P (with enhanced thermal pad) –SOP-8-P (with enhanced thermal pad) Lead Free Available (RoHS Compliant) 1.2.6 Keyboard System – IT8512 Universal Keyboard Controller 8032 Embedded Controller - Twin Turbo version/3-stage pipeline - 9.2 MHz for EC domain and 8032 internal timer - Variable frequency range to gain the maximum 8032 code-fetch performance -Instruction set compatible with standard 8051/2 LPC Bus Interface...
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- Supports Memory read/write - Supports FWH read/write -Serial IRQ Flash Interface - Behaves as a LPC/FWH memory device (HLPC) to the host SouthBridge - Supports external serial flash with 32.3~64.5 - Up to 16M bytes Flash space shared by the host and EC side (serial flash) SM Bus Controller - SM Bus spec.
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System Wake Up Control - Modem RI# wake up - Telephone RING# wake up - IRQ/SMI routing EC Wake Up Control - 40 external/internal wake up events Interrupt Controller - 48 interrupt events to EC - Fixed priority Timer / Watch Dog Timer - 3 16-bit multi-function timers inside 8032, which is based on EC clock - 1 watch dog timer inside 8032, which is based...
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- 1 external WDT in ETWD module, which is based on 32.768 k clock source UART -1 full duplex UART inside 8032 ACPI Power Management Channel - 2 Power management channels - Compatible and enhanced mode Battery-backed SRAM - Supports 64-byte battery-backed memory space - Supports power-switch circuit GPIO...
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External GPIO Controller (EGPC) - Communicate with 4 IT8301 chips -Each IT8301 supports 38 GPIO ports KBC Interface - 8042 style KBC interface - Legacy IRQ1 and IRQ12 - Fast A20G and KB reset - 12 ADC channels (8 external) - 10-bit resolution (+/- 4LSB) - Digital filter for noise reduction - 6 DAC channels...
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- 8 PWM channels - Base clock frequency is 32.768 kHz - 8 duty cycle resolution - 8/16-bit common input clock prescaler - 4 prescalers for 8 PWM output used for devices with different frequencies - 2 Tachometers for measuring fan speed - Complete resolution 256 PWM output supported.
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KB Matrix Scan - Hardware keyboard scan - 18x8 keyboard matrix scan 1.2.7 System SPI Flash Memory (BIOS) –EN25F16 The EN25F16 is a 16M-bit (2048K-byte) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
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Low power consumption - 5 mA typical active current - 1 μA typical power down current Uniform Sector Architecture: - 512 sectors of 4-Kbyte - 32 blocks of 64-Kbyte - Any sector or block can be erased individually Software and Hardware Write Protection: - Write Protect all or portion of memory viasoftware - Enable/Disable protection with WP# pin High performance program/erase speed...
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Lockable 256 byte OTP security sector Minimum 100K endurance cycle Package Options - 8 pins SOP 200mil body width - 8 contact VDFN - 8 pins PDIP - 16 pin SOP 300mil body width - All Pb-free packages are RoHS compliant 1.2.8 Card Reader - RTS5159 The RTS5159 is an ultimate throughput USB 2.0 compliant card reader controller that integrates USB 2.0 Transceiver, MCU, SIE, regulators and memory card access units into a single chip.
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The RTS5159 integrates 3.3V-to-1.8V regulator, clock generation circuitry and MOSFET, and could dramatically reduce the system BOM cost. Compliant with Universal Serial Bus Specification Revision 2.0 Compliant with USB Mass Storage Class Bulk only Transport Specification Rev. 1.0 Support High-speed (480Mbps) and Full-speed (12Mbps) Data Transfer USB bus power operation Support Control, Bulk IN / OUT data pipes Support the following memory card interfaces:...
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Support hardware CRC (Cyclic Redundancy Check) function Programmable clock rate for flash memory card interfaces Support MS-PRO v1.02 Support MS v1.43 Support MS PRO-HG Duo v1.01 Support SD version 2.0 Support MMC version 4.2...
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1.2.10 RGMII LAN PHY - RTL8111D The Realtek RTL8111D-GR/RTL811DL-GR Gigabit Ethernet controller combines a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the RTL8111D/RTL8111DL offers high-speed transmission over CAT5 UTP cable or CAT3 UTP (10Mbps only) cable.
1.3 Other Function 1.3.1 Hot Key Function Keys Feature Meaning Combination Fn + F1 Wireless LAN ON/OFF Enable or Disable Wireless LAN Function Fn + F2 Bluetooth ON/OFF Enable or Disable Bluetooth Function Fn + F3 Volume down Audio Volume down Fn + F4 Volume up Audio Volume up...
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1.3.2 Power on/off/Suspend/Resume Button 1.3.2.1 APM Mode At APM mode, Power button is on/off system power. 1.3.2.2 ACPI Mode At ACPI mode, Windows power management control panel set power button behavior. You could set "standby", "power off" or "hibernate"(must enable hibernate function in power Management) to power button function.
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2. Standby 3. Off 4. Hibernate (must enable hibernate function in power management 1.3.4 LED Indicators System has six status LED indicators to display system activity, which include six above Front Bezel and MMB LED indicators.
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1.3.4.1 Six LED Indicators System State LED Indicators Definition S1/S2 Location Front Bezel function status Battery Charge LED Battery Full Charged Left 1 Battery charging Blue Blue Blue Blue Battery Critical Low Blue Blink Blue Blink Blue Blink Blue Blink Wlan WLAN Enable Blue...
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1.3.5 Battery status 1.3.5.1 Battery Warning System also provides Battery capacity monitoring and gives user a warning so that users have chance to save his data before battery dead. Also, this function protects system from mal-function while battery capacity is low. Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds.
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1.3.6 Fan Power on/off Management 1.3.6.1 CPU Fan FAN is controlled by W83L951AD embedded controller-using F75385 to sense CPU temperature and W83L951AD PWM control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature will get faster Fan Speed.
1.5 Power Management The 9270D system has built in several power saving modes to prolong the battery usage. User can enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing F2 key). Following are the descriptions of the power management modes supported.
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- LCD: backlight off - HDD: spin down Suspend to DRAM The most chipset of the system is entering power down mode for more power saving. In this mode, the following is the status of each device: -- CPU: off -- Twister K: Partial off -- VGA: Suspend -- New Card: Suspend...
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1.5.2 Battery Only Power off Mode The 9270D system has built in Battery only power off mode to prolong the battery usage. In this mode, Universal Keyboard Controller (KBC) will be power off. In addition, the system leakage current shall be less than 0.5mA;...
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1.6.3 9270D Product Spec-1 ITEM CATEGORY DESCRIPTION Type Intel Capella PM Package 45/35W (Processor/chipset SOC) Socket Socket-P Speed Others Assembling Capability Distribution configurable Brand Phoenix Size of EEPROM System BIOS BIOS Architecture Others Brand & Model Name: North None Bridge Chipset Brand &...
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1.6.3 9270D Product Spec-2 ITEM CATEGORY DESCRIPTION Type (UMA or Discrete) Discrete Interface PCI-E VIDEO Brand & Model Name ATI M96-M2 Pro+ CONTROLLER Marketing Name ATI Mobility Radeon™ HD 4650 Others 128bit memory bus/ No TV Out Type gDDRIII No. of Vram Chips...
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1.6.3 9270D Product Spec-3 ITEM CATEGORY DESCRIPTION Size 18.4"W Type DISPLAY Resolution 1680x945 HD+ 1920x1080 FHD Others Height 5.6mm Pitch 18.45mm Stroke 2.6mm KEYBOARD Width 339mm Layout US/UI Others Type Underplastic touchpad without scroll bar POINTING Number of Button DEVICE...
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1.6.3 9270D Product Spec-4 ITEM CATEGORY DESCRIPTION Ejection Type Memory Card Type of Card Support SD/MS/MS Pro/MMC Reader Others 3 (USB 2.0) USB/e-SATA RJ-11 RJ-45 Headphone S/PDIF Microphone Line In DC Input Analog VGA Port I/O Port DVI-D DVI-I S-Video Out...
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1.6.3 9270D Product Spec-5 ITEM CATEGORY DESCRIPTION Number of Quick Key Quick Key Definition Number of Indicator Indicator WLAN/BT/power/battery charge/cap Definition lock/num lock/HDD & ODD Interface Type & Speed Modem Form Factor Assembling Capability Others Interface LAN Phy Speed 10/100/1000 Mbps...
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1.6.3 9270D Product Spec-6 ITEM CATEGORY DESCRIPTION Type Li-Ion Cylinder Number of Cell 9 cell Battery Pack Capacity 6600mAH/11.1V (9 cell) Battery Life Assembling Capability user Swappable Type Universal AC adaptor Wattage 90W/120W Input Voltage 100V ~ 240V AC Adapter...
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1.6.3 9270D Product Spec-7 ITEM CATEGORY DESCRIPTION Microsoft LOGO Windows Logo Vista Premium SP1 Windows 7 Regulation Safety Green Product ROHS Coverage...
2. System View and Disassembly 2.1 System View 2.1.1 Left-side View Kensington Lock CRT Connector RJ45 Connector HDMI Connector ESATA+USB Connector USB Ports Card Reader Connector Express Card Connector...
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2.1.2 Right-side View Headphone out MIC In SPDIF Connector USB Port Power Jack 2.1.3 Rear View Ventilation Openings...
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2.1.4 Bottom View CPU & DDR3 SO-DIMM & Mini Express Card Battery Park 2.1.5 Top-open View LCD Screen Power Button Internal MIC ○ Touch Pad ○ Keyboard Speaker Web Camera...
2.2 Tools Introduction 1. Minus screw driver for notebook assembly & disassembly. 2 mm 2 mm 2. Auto screw driver for notebook assembly & disassembly. Bit Size Screw Size Tooling Tor. Bit Size 1. M2.0 Auto-Screw driver 2.0-2.5 kg/cm...
2.3 System Disassembly The section discusses at length each major component for disassembly/reassembly and show corresponding illustrations.Use the chart below to determine the disassembly sequence for removing components from the notebook. NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power.
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2.3.1 Battery Pack Disassembly 1. Carefully put the notebook upside down. 2. Slide two release lever outwards to the “unlock” ( ) position ( ), while take the battery pack out of the compartment ( ). (Figure 2-1) Figure 2-1 Remove the battery pack Reassembly 1.
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2.3.2 CPU Disassembly 1. Remove the battery pack. (Refer to section 2.3.1 Disassembly) 2. Remove eight screws fastening the CPU cover. (Figure 2-2) 3. Remove six spring screws that secure the heatsink upon the CPU and remove three screws fastening the fan, then disconnect the fan’s power cord from system board.
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4. To remove the existing CPU, loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU. (Figure 2-4) Figure 2-4 Remove the CPU Reassembly 1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into the holes.
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2.3.3 DDR3-SDRAM Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (See section 2.3.1 Disassembly) 2. Remove eight screws fastening the CPU cover. (Refer to step 2 of section 2.3.2 Disassembly) Figure 2-5 Remove the SO-DIMM 3. Pull the retaining clips outwards ( ) and remove the SO-DIMM ( ). (Figure 2-5) Reassembly 1.
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2.3.4 HDD Disassembly 1. Carefully put the notebook upside down. Remove the battery pack and . (Refer to section 2.3.1 Disassembly) 2. Remove two screws fastening the HDD cover. (Figure 2-6) 3. Lift the HDD module out and disconnect the HDD connector. (Figure 2-7) Figure 2-7 Remove HDD module Figure 2-6 Remove HDD cover Reassembly...
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2.3.5 ODD Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly) 2. Remove one screw fastening the ODD. (Figure 2-9) 3. Insert a small rod, such as a straightened paper clip, into ODD’s manual eject hole ( ) and push firmly to release the tray.
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2.3.6 Keyboard Disassembly 1. Remove the battery pack. (Refer to section 2.3.1 Disassembly) 2. Remove four screws fastening the keyboard cover, then remove the keyboard cover. (figure 2-10) 3. Remove three screws fastening the keyboard. (Figure 2-11) Figure 2-10 Remove the keyboard cover Figure 2-11 Remove four screws...
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4. Slightly turn over the keyboard and disconnect the cable from the system board to detach the keyboard. (Figure 2-12) Figure 2-12 Remove the keyboard Reassembly 1. Reconnect the keyboard cable and fit the keyboard back into place, then secure the keyboard with three screws.. 2.
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2.3.7 LCD ASSY Disassembly 1. Remove the battery pack, CPU, DDR3, HDD, ODD and keyboard. (See sections 2.3.1~2.3.6 Disassembly) 2. Remove twenty-seven screws and disconnect one cable. (Figure 2-13) 3. Turn over the unit, remove nine screws and disconnect the touch pad cable, then remove the top cover. (Figure 2-14) Figure 2-13 Remove twenty-seven screws Figure 2-14 Remove the top cover and disconnect one cable...
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4. Remove nine screws and carefully pull the antenna wire and two cables out. Then free the LCD assembly. (Figure 2-15) Figure 2-15 Free the LCD assembly Reassembly 1. Attach the LCD assembly to the base unit and secure with nine screws. Reconnect the antenna wires and two cables. 2.
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2.3.8 Inverter Board Disassembly 1. Remove the LCD assembly. (Refer to section 2.3.7 Disassembly) 2. Remove six screws fastening the LCD cover. (Figure 2-16) 3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process as figure 1-20 arrowhead hints until the cover is completely separated from the housing.
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5. Disconnect two cables, then remove the inverter board. (Figure 2-18) Figure 2-18 Remove the inverter board Reassembly 1. Replace the inverter board and reconnect two cables. 2. Replace the LCD panel and inverter board into the LCD housing, then secure with nine screws. 3.
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2.3.9 LCD Panel Disassembly 1. Remove the LCD assembly and inverter board. (Refer to section 2.3.7 and 2.3.8 Disassembly) 2. Remove eight screws that secure the LCD brackets. (Figure 2-19) 3. Disconnect LCD cable to free the panel. (Figure 2-20) Figure 2-19 Remove eight screws Figure 2-20 Free the LCD panel Reassembly...
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2.3.10 Audio Jack Board Disassembly 1. Remove the LCD assembly. (Refer to sections 2.3.7 Disassembly) 2. Remove six screws fastening the shielding. Then remove the shielding. (Figure 2-21) 3. Remove one screw and disconnect two cables, then remove the audio jack board. (Figure 2-22) Figure 2-21 Remove the shielding Figure 2-22 Remove the audio jack board Reassembly...
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2.3.11 ODD Transfer Board Disassembly 1. Remove the LCD assembly. (Refer to sections 2.3.7 Disassembly) 2. Remove the shielding. (See step 2 of section 2.3.10 Disassembly) 3. Remove one screw fastening the ODD transfer board, the remove it flatly. (Figure 2-23) Figure 2-23 Remove the ODD transfer board Reassembly 1.
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2.3.12 System Board Disassembly 1. Remove the LCD assembly, audio jack board and ODD transfer board. (Refer to sections 2.3.7, 2.3.10&2.3.11 Disassembly) 2. Remove three screws fastening the system board. (Figure 2-24) 3. Remove two screws fastening the HDD cable and disconnect two cables, the free the system board. (Figure 2-25) Figure 2-24 Remove five screws Figure 2-25 Free the system board Reassembly...
4. Pin Descriptions of Ibex Peak-M 4.1 Digital Media Interface Signals Name Type Description DMI0TXP, Digital Media Interface Differential Transmit Pair 0 DMI0TXN DMI0RXP, Digital Media Interface Differential Receive Pair 0 DMI0RXN DMI0RXP, Digital Media Interface Differential Transmit Pair 1 DMI1RXN DMI0RXP, Digital Media Interface Differential Receive Pair 1...
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4.3 Firmware Hub Interface Signals Name Type Description FWH[3:0] / Firmware Hub Signals. These signals are multiplexed with LAD[3:0] the LPC address signals. FWH4 / Firmware Hub Signals. This signal is multiplexed with the LFRAME# LPC LFRAME# signal. Initialization 3.3 V: INIT3_3V# is asserted by the Ibex Peak for 16 PCI clocks to reset the processor.
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4.4 PCI Interface Signals –Table 1 Name Type Description PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] AD[31:0] contain data. The Ibex Peakwill drive all 0s on AD[31:0] during the address phase of all PCI Special Cycles.
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4.4 PCI Interface Signals –Table 2 Name Type Description Device Select: The Ibex Peak asserts DEVSEL# to claim a PCI transaction. As an output, the Ibex Peak asserts DEVSEL# when a PCI master peripheral attempts an access to an internal Ibex Peak address or an address destined for DMI (main memory or graphics).
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4.4 PCI Interface Signals –Table 3 Name Type Description Initiator Ready: IRDY# indicates the Ibex Peak's ability, as an initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted.
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4.4 PCI Interface Signals –Table 4 Name Type Description Stop: STOP# indicates that the Ibex Peak, as a target, is requesting the initiator to stop the current transaction. STOP# causes the Ibex Peak, as an initiator, to stop the current STOP# transaction.
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4.4 PCI Interface Signals –Table 5 Name Type Description Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The Ibex Peak drives PERR# when it detects a parity error. The Ibex Peak can PERR# either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR#...
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4.4 PCI Interface Signals –Table 6 Name Type Description PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR of the primary interface PLTRST# signal and the PCIRST# state of the Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6).
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4.5 Serial ATA Interface Signals–Table 1 Name Type Description Serial ATA 0 Differential Transmit Pairs: These are outbound high-speed differential signals to Port 0. In SATA0TXP compatible mode, SATA Port 0 is the primary master of SATA SATA0TXN Controller 1. Serial ATA 0 Differential Receive Pair: These are inbound high-speed differential signals from Port 0.
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4.5 Serial ATA Interface Signals–Table 2 Name Type Description Serial ATA 2 Differential Receive Pair: These are inbound high-speed differential signals from Port 2. In compatible SATA2RXP mode, SATA Port 2 is the primary slave of SATA Controller 1 SATA2RXN NOTE: SATA Port 2 may not be available in all PCH SKUs.
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4.5 Serial ATA Interface Signals–Table 3 Name Type Description Serial ATA 5 Differential Transmit Pair: These are outbound SATA5TXP high-speed differential signals to Port 5. In compatible mode, SATA SATA5TXN Port 5 is the secondary master of SATA Controller 2 Serial ATA 5 Differential Receive Pair: These are inbound high- SATA5RXP speed differential signals from Port 5.
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4.5 Serial ATA Interface Signals–Table 4 Name Type Description Serial ATA 3 General Purpose: Same function as SATA0GP, except for SATA Port 3. If interlock switches are not required, this SATA3GP / pin can be configured as GPIO37. NOTE: This signal can also be GPIO37 used as GPIO37.
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4.6 LPC Interface Signals Name Type Description LPC Multiplexed Command, Address, Data: For LAD[3:0], LAD[3:0] / internal pull-ups are provided. FWH[3:0] LPC Frame: LFRAME# indicates the start of an LPC cycle, LFRAME# / or an abort. FWH4 LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access.
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4.7 Interrupt Signals Name Type Description Serial Interrupt Request: This pin implements the serial I/OD SERIRQ interrupt protocol. PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15.
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4.8 USB Interface Signals –Table 1 Name Type Description Universal Serial Bus Port [1:0] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1. These ports can be routed to UHCI USBP0P, controller #1 or the EHCI controller #1. USBP0N, NOTE: No external resistors are required on these signals.
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4.8 USB Interface Signals –Table 2 Name Type Description Universal Serial Bus Port [7:6] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 6 and 7. These ports can be routed to UHCI USBP6P, controller #4 or the EHCI controller #2. USBP6N, NOTE: No external resistors are required on these signals.
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4.8 USB Interface Signals –Table 3 Name Type Description Universal Serial Bus Port [13:12] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 13 and 12. These ports can be routed to UHCI USBP12P, controller #7 or the EHCI controller #2. USBP12N, NOTE: No external resistors are required on these signals.
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4.9 Power Management Interface Signals –Table 1 Name Type Description Platform Reset: The Ibex Peak asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, Processor, etc.). The Ibex Peak asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register CF9h).
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4.9 Power Management Interface Signals –Table 2 Name Type Description S5 Sleep Control: SLP_S5# is for power plane control. This signal is used to shut power off to all non-critical systems SLP_S5# / GPIO63 when in the S5 (Soft Off) states. Pin may also be used as GPIO63 Manageability Sleep State Control: This signal is used to control power planes to the Intel®...
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4.9 Power Management Interface Signals –Table 3 Name Type Description Power OK: When asserted, PWROK is an indication to the Ibex Peak that all of its core power rails have been stable for 10 ms. PWROK can be driven asynchronously. When PWROK is negated, the Ibex Peak asserts PLTRST#.
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4.9 Power Management Interface Signals –Table 4 Name Type Description System Reset: This pin forces an internal reset after being debounced. The Ibex Peak will reset immediately if the SMBus SYS_RESET# is idle; otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before forcing a reset on the system.
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4.9 Power Management Interface Signals –Table 5 Name Type Description PCI Express* Wake Event: Sideband wake signal on PCI WAKE# Express asserted by components requesting wake up. Suspend Status: This signal is asserted by the Ibex Peak to indicate that the system will be entering a low power state soon.
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4.9 Power Management Interface Signals –Table 6 Name Type Description Battery Low: Mobile only signal is an input from the battery BATLOW# to indicate that there is insufficient power to boot the system. (Mobile Only) / Assertion will prevent wake from S3–S5 state. This signal can GPIO72 also be enabled to cause an SMI# when asserted.
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4.10 Processor Interface Signals Name Type Description Keyboard Controller Reset CPU: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the PCH’s other sources of INIT#. When the PCH detects the assertion of this signal, INIT# is generated for RCIN# 16 PCI clocks.
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4.12 System Management Interface Signals Name Type Description Intruder Detect: This signal can be set to disable system if box detected open. This signal’s status is readable, so it can be INTRUDER# used like a GPI if the Intruder Detection is not needed. System Management Link 0 Data: SMBus link to external I/OD SML0DATA...
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4.13 Real Time Clock Interface Name Type Description Crystal Input 1: This signal is connected to the 32.768 kHz Special crystal. If no external crystal is used, then RTCX1 can be RTCX1 driven with the desired clock rate. Crystal Input 2: This signal is connected to the 32.768 kHz Special crystal.
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4.14 Miscellaneous Signals Name Type Description Internal Voltage Regulator Enable: This signal enables the internal 1.05 V regulators. INTVRMEN This signal must be always pulled-up to VccRTC. Speaker: The SPKR signal is the output of counter 2 and is internally “ANDed” with Port 61h bit 1 to provide Speaker Data Enable.
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4.15 Intel® High Definition Audio Link Signals –Table 1 Name Type Description Intel® High Definition Audio Reset: Master hardware reset HDA_RST# to external codec(s). Intel High Definition Audio Sync: 48 kHz fixed rate sample sync to the codec(s). Also used to encode the stream number. NOTE: This signal is sampled as a functional strap.
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4.15 Intel® High Definition Audio Link Signals –Table 2 Name Type Description High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an active low signal. When deasserted the external docking switch is in isolate mode.
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4.16 Controller Link Signals Name Type Description CL_RST1# Controller Link Reset 1: Controller Link reset that connects (Mobile Only) / to a Wireless LAN Device supporting Intel® Active TP20 (Desktop Management Technology. Only) CL_CLK1 Controller Link Clock 1: bi-directional clock that connects to (Mobile Only) / a Wireless LAN Device supporting Intel®...
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4.18 Intel® Quiet System Technology Signals Name Type Description Fan Pulse Width Modulation Outputs: Pulse Width Modulated duty cycle output signal that is used for Intel® Quiet System Technology. PWM[3:0] When controlling a 3-wire fan, this signal controls a power (Desktop Only) OD O transistor that, in turn, controls power to the fan.
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4.19 JTAG Signals Name Type Description Test Clock Input (TCK): The test clock input provides the JTAG_TCK clock for the JTAG test logic. Test Mode Select (TMS): The signal is decoded by the Test JTAG_TMS Access Port (TAP) controller to control test operations. Test Data Input (TDI): Serial test instructions and data are JTAG_TDI received by the test logic at TDI.
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4.20 Dual Channel NAND Interface –Table 1 Name Type Description Data Input/Output: The bidirectional I/O used to transfer command, address and data to and from NAND device. Data is output during write operations and input during read NV_DQ[15:0] / NV_IO[15:0] operations.
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4.20 Dual Channel NAND Interface –Table 2 Name Type Description Source Synchronous Mode: Write Read[1:0]# Indicates owner of the NV_DQ / NV_IO and NV_DQS signals. ‘1’, NV_DQ / NV_IO and NV_DQS are driven by IBX NAND Controller. NV_WR#[1:0] ‘0’, NV_DQ / NV_IO and NV_DQS are driven by the NAND /NV_RE#[1:0] device.
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4.21 Clock Interface Signals –Table 1 Name Type Description 133 MHz differential reference clock from a clock chip in CLKIN_BCLK_P, Buffer-Through Mode. Unused when Integrated Clock CLKIN_BCLK_N Generation is enabled. CLKOUT_BCLK0_P 133MHz Differential output to Processor or 100 MHz PCIe* Gen 1.1 specification differential output to PCI Express CLKOUT_PCIE8_P, devices.
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4.21 Clock Interface Signals –Table 2 Name Type Description CLKIN_DOT96P, 96MHz differential reference clock from a clock chip. CLKIN_DOT96N Connection for 25MHz crystal to Ibex Peak oscillator circuit. XTAL25_IN Connection for 25MHz crystal to Ibex Peak oscillator circuit. XTAL25_OUT Single-ended 14.31818MHz reference clock driven by a clock REFCLK14IN chip.
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4.21 Clock Interface Signals –Table 3 Name Type Description PCIECLKRQ0# / GPIO73, PCIECLKRQ1# / GPIO18, PCIECLKRQ2# / GPIO20, Clock Request Signals for PCI Express 100 MHz Clocks Can PCIECLKRQ3# / instead by used as GPIOs GPIO25, PCIECLKRQ4# / NOTE: External Pull-up Resistor required if used for GPIO26, CLKREQ# functionality PCIECLKRQ5# /...
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4.21 Clock Interface Signals –Table 4 Name Type Description Configurable as a GPIO or as an Intel Management Firmware programmable output clock which can be configured as one of the following: CLKOUTFLEX0 / -33 MHz GPIO64 -14.31818 MHz -DC Output logic ‘0’ - (Default) NOTE: Default clock setting requires no ME FW configuration.
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4.22 LVDS Interface Signals –Table 1 Name Type Description LVDSA_DATA LVDS Channel A differential data output - positive [3:0] LVDSA_DATA LVDS Channel A differential data output -negative #[3:0] LVDS Channel A differential clock output - positive LVDSA_CLK LVDS Channel A differential clock output - negative LVDSA_CLK# LVDSB_DATA LVDS Channel B differential data output - positive...
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4.22 LVDS Interface Signals –Table 2 Name Type Description EDID support for flat panel display L_DDC_DATA Control signal (clock) for external SSC clock chip control – L_CTRL_CLK optional Control signal (data) for external SSC clock chip control – L_CTRL_DAT optional LVDS Panel Power Enable: Panel power control enable control for LVDS.
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4.23 Analog Display Interface Signals Name Type Description RED Analog Video Output: This signal is a CRT Analog CRT_RED video output from the internal color palette DAC. GREEN Analog Video Output: This signal is a CRT Analog CRT_GREEN video output from the internal color palette DAC. BLUE Analog Video Output: This signal is a CRT Analog CRT_BLUE video output from the internal color palette DAC.
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4.24 Intel Flexible Display Interface Signals Name Type Description Display Link 1 positive data in FDI_RXP[3:0] Display Link 1 negative data in FDI_RXN[3:0] Display link 1 Frame sync FDI_FSYNC[0] Display link 1 Line sync FDI_LSYNC[0] Display Link 2 positive data in FDI_RXP[7:4] Display Link 2 negative data in FDI_RXN[7:4]...
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4.26 Digital Display Interface Signals –Table 1 Name Type Description Port B: Capable of SDVO / HDMI / DVI / DisplayPort SDVO DDPB_[0]P: red DDPB_[1]P: green DDPB_[2]P: blue DDPB_[3]P: clock HDMI / DVI Port B Data and Clock Lines DDPB_[0]P: TMDSB_DATA2 DDPB_[3:0]P DDPB_[1]P: TMDSB_DATA1 DDPB_[2]P: TMDSB_DATA0...
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4.26 Digital Display Interface Signals –Table 2 Name Type Description Port B: Capable of SDVO / HDMI / DVI / DisplayPort SDVO DDPB_[0]N: red complement DDPB_[1]N: green complement DDPB_[2]N: blue complement DDPB_[3]N: clock complement HDMI / DVI Port B Data and Clock Line Complements DDPB_[0]N: TMDSB_DATA2B DDPB_[3:0]N DDPB_[1]N: TMDSB_DATA1B...
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4.26 Digital Display Interface Signals –Table 3 Name Type Description SDVO_INTP: Serial Digital Video Input Interrupt SDVO_INTP SDVO_INTN: Serial Digital Video Input Interrupt SDVO_INTN Complement. SDVO_TVCLKINP: Serial Digital Video TVOUT SDVO_TVCLK Synchronization Clock. SDVO_TVCLKINN: Serial Digital Video TVOUT SDVO_TVCLK Synchronization Clock Complement. SDVO_STALL SDVO_STALLP: Serial Digital Video Field Stall.
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4.26 Digital Display Interface Signals –Table 4 Name Type Description Port C: Capable of HDMI / DVI / DisplayPort HDMI / DVI Port C Data and Clock Line Complements DDPC_[0]N: TMDSC_DATA2B DDPC_[1]N: TMDSC_DATA1B DDPC_[2]N: TMDSC_DATA0B DDPC_[3]N: TMDSC_CLKB DDPC_[3:0]N DisplayPort Port C Complements DDPC_[0]N: Lane 0 complement DDPC_[1]N: Lane 1 complement DDPC_[2]N: Lane 2 complement...
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4.26 Digital Display Interface Signals –Table 5 Name Type Description Port D: Capable of HDMI / DVI / DP HDMI / DVI Port D Data and Clock Lines DDPD_[0]P: TMDSC_DATA2 DDPD_[1]P: TMDSC_DATA1 DDPD_[2]P: TMDSC_DATA0 DDPD_[3]P: TMDSC_CLK DDPD_[3:0]P DisplayPort Port D DDPD_[0]P: Display Port Lane 0 DDPD_[1]P: Display Port Lane 1 DDPD_[2]P: Display Port Lane 2...
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4.27 General Purpose I/O Signals –Table 1 Note: 1. GPIO Configuration registers within the Core Well are reset whenever PWROK is deasserted. 2. GPIO Configuration registers within the Suspend Well are reset when RSMRST# is asserted, CF9h reset (06h or 0Eh) event occurs, or SYS_RST# is asserted. 3.
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4.27 General Purpose I/O Signals –Table 2 Power Blink Name Type Tolerance Default Description Well Capability GPIO59 3.3 V Suspend Native Multiplexed with OC[0]# (Note 12) GPIO58 3.3 V Suspend Native Multiplexed with SML1CLK GPIO57 3.3 V Suspend Unmultiplexed GPIO56 3.3 V Suspend Native...
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4.27 General Purpose I/O Signals –Table 3 Power Blink Name Type Tolerance Default Description Well Capability GPIO35 3.3 V Core Unmultiplexed. GPIO34 3.3 V Core Multiplexed with STP_PCI# Multiplexed with HDA_DOCK_EN# GPIO33 3.3 V Core (Mobile Only) (Note 4) GPO, Unmultiplexed (Desktop Only) Native GPIO32...
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4.27 General Purpose I/O Signals –Table 4 Power Blink Name Type Tolerance Default Description Well Capability GPIO20 3.3 V Core Native Multiplexed with PCIECLKRQ2# GPIO19 3.3 V Core Multiplexed with SATA1GP GPIO18 3.3 V Core Native Yes (Note 6) Multiplexed with PCIECLKRQ1# Multiplexed with TACH0.
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4.27 General Purpose I/O Signals NOTES: All GPIOs can be configured as either input or output. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI, but not both. Some GPIOs exist in the VccSus3_3 power plane.
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4.27 General Purpose I/O Signals NOTES: For GPIOs where GPIO vs. Native Mode is configured via SPI Soft Strap, the corresponding GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL bits for these GPIOs may change to reflect the Soft-Strap configuration even though GPIO Lockdown Enable (GLE) bit is set.
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4.28 Manageability Signals -1 The following signals can be optionally utilized by Ibex Peak Management engine supported applications and appropriately configured by Management Engine firmware. When configured and utilized as a Manageability function, the associated host GPIO functionality is no longer available.
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4.28 Manageability Signals -2 Name Type Description Used as an alert (active low) to indicate to the external SATA5GP / GPIO49 / controller (e.g EC or SIO) that temperatures are out of range for the PCH or Graphics/Memory Controller or the Processor TEMP_ALERT# Core.
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4.29 Power and Ground Signals –Table 1 Name Description Decoupling: This signal is for RTC decoupling only. This DcpRTC signal requires decoupling. Decoupling: Internally generated 1.5V powered off of Suspend Well. This signal requires decoupling. Decoupling is DcpSST required even if this feature is not used. Decoupling: 1.05 V Suspend well supply that is supplied DcpSus internally by Internal VRs.
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4.29 Power and Ground Signals –Table 1 Name Description Decoupling: This signal is for RTC decoupling only. This DcpRTC signal requires decoupling. Decoupling: Internally generated 1.5V powered off of Suspend Well. This signal requires decoupling. Decoupling is DcpSST required even if this feature is not used. Decoupling: 1.05 V Suspend well supply that is supplied DcpSus internally by Internal VRs.
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4.29 Power and Ground Signals –Table 2 Name Description Power supply for DMI. 1.1 V or 1.05 V based on the processor used. Please refer to the VccDMI respective processor documentation to find the appropriate voltage level. 1.05 V supply for LAN controller logic. This is a separate power plane that may or may not be powered in S3–S5 states.
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4.29 Power and Ground Signals –Table 3 Name Description 1.05 V supply for Display PLL A Analog Power. This power is VccADPLLA supplied by the core well. 1.05 V supply for Display PLL B Analog Power. This power is VccADPLLB supplied by the core well.
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4.29 Power and Ground Signals –Table 4 Name Description Non-Critical To Function. These pins are for package mechanical reliability. TP22_NCTF Note: These pins should be connected to Ground. 1.05 V Analog power supply for internal clock PLL. This requires a filter and power is supplied by the core well. VccAClk NOTE: This pin can be left as no connect in On-Die VR enabled mode (default).
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4.30 Functional Strap Definitions –Table 1 The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations (except as noted), and then revert later to their normal usage. To invoke the associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled.
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4.30 Functional Strap Definitions –Table 2 The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations (except as noted), and then revert later to their normal usage. To invoke the associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled.
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4.30 Functional Strap Definitions –Table 3 When Name Usage Comment Sampled The signal has a weak internal pull-up. Note: the internal pull-up is disabled after PCIRST# de- asserts. If the signal is sampled low, this indicates that the system is Top-Block Swap Rising edge of strapped to the “topblock swap”...
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4.30 Functional Strap Definitions –Table 4 When Name Usage Comment Sampled This Signal has a weak internal pull-up. Note: the internal pull-up is disabled after PCIRST# de- asserts. This field determines the destination of accesses to the BIOS memory range. Also controllable via Boot BIOS Destination bit (Chipset Config Registers:Offset 3410h:bit 11).
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4.30 Functional Strap Definitions –Table 5 When Name Usage Comment Sampled This Signal has a weak internal pull-up. Note: the internal pull-up is disabled after PCIRST# de-asserts. This field determines the destination of accesses to the BIOS memory range. Also controllable via Boot BIOS Destination bit (Chipset Config Registers:Offset 3410h:bit 10).
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4.30 Functional Strap Definitions –Table 6 When Name Usage Comment Sampled This Signal has a weak internal pull-up. Note: the internal pull-up is disabled after PCIRST# de-asserts. This field determines the destination of accesses to the BIOS memory range. Also controllable via Boot BIOS Destination bit (Chipset Config Registers:Offset 3410h:bit 10).
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4.30 Functional Strap Definitions –Table 7 When Name Usage Comment Sampled This Signal has a weak internal pull-up. Note: the internal pull-up is disabled after ESI Strap Rising edge of PCIRST# de-asserts.Tying this strap low configures DMI for GNT2#/ (Server Only) PWROK ESI compatible operation.
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4.30 Functional Strap Definitions –Table 8 When Name Usage Comment Sampled Rising edge of This signal has a weak internal pull-down resistor. This signal Functionality SPI_MOSI MEPWROK must be sampled low. Disable Rising edge of Termination This signal has a weak internal pull-down. NV_CLE PWROK Voltage...
5. System Block Diagram U705 U704 PCIEx16 DDR3 1066MHZ PROCESSOR Nvida ARRANDALE M96-PRO+ HDMI DMI2 SATA SATA ODD INT MIC SATA SATA HDD EXT MIC Azalia AUDIO SATA ESATA/USB CODEC LINE OUT/SPIDF COBO U712 ALC663 Headphone WEBCAM L-speaker X10 Receiver APA2031 R-speaker IBEX PEAK-M...
6. Trouble Shooting 6.1 No Power (*1) 6.2 No Display (*2) 6.3 Graphics Controller Failure LCD No Display 6.4 External Monitor No Display 6.5 Memory Failure 6.6 Keyboard (K/B) or Touch-Pad (T/P) Failure 6.7 Hard Disk Drive Failure 6.8 ODD Failure 6.9 USB Ports Failure 6.10 Audio Failure 6.11 LAN Failure...
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*1: No Power Definition Base on ACPI Spec. We define the no power as while we press the power button, the system can’t leave S5 status or none the PG signal send out from power supply. Judge condition: Check whether there are any voltage feedback control to turn off the power. Check whether no CPU power will cause system can’t leave S5 status.
6.1 No Power When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. Check following parts and signals: No Power Parts: Signals: PJ702 1908_CSSN Board-level PF702 1908_CSSP Is the Troubleshooting EL709 notebook connected ADINP...
6.2 No Display There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good. Refer to port error code No Display description section to find out which part is causing System Monitor the problem.
6.3 Graphics Controller Failure LCD No Display There is no display or picture abnormal on LCD although power-on-self-test is passed. Graphics Controller Failure LCD No Display Check if 1. Confirm LCD panel or monitor is good Re-soldering. J1 are cold and check the cable are connected solder? properly.
6.4 External Monitor No Display There is no display or picture abnormal on CRT monitor, but it is OK for LCD. External Monitor No Display 1. Confirm monitor is good and check Check if J701 Board-level Re-soldering. the cable are connected properly. is cold solder? Troubleshooting 2.
6.5 Memory Failure Extend DDR2 SO-DIMM is failure or system hangs up. Memory Failure One of the following components or signals on the motherboard 1. Check the extend SO-DIMM module is may be defective ,Use an oscilloscope to check the signals or installed properly.
6.6 Keyboard (K/B) or Touch-Pad (T/P) Failure Error message of keyboard or touch-pad test error is shown or any key does not work. Keyboard (K/B) or Touch-Pad (T/P) Failure Check J3, J4 Re-soldering. Board-level for cold solder? Troubleshooting Is K/B or T/P cable connected to notebook Correct it.
6.7 Hard Disk Drive Failure Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to hard disk. Hard Disk Drive Failure 1. Check if BIOS setup is OK?. Board-level 2. Try another working drive. Troubleshooting One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace...
6.8 ODD Failure An error message is shown when reading data from ODD drive. ODD Failure Board-level 1. Try another known good compact disk. Troubleshooting 2. Check install for correctly. One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement.
6.9 USB Ports Failure An error occurs when a USB I/O device is installed. USB Ports Failure Check if the USB device is installed properly. Board-level Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope Troubleshooting to check the following signal or replace the parts one at a time Test...
6.10 Audio Failure No sound from speaker after audio driver is installed. Audio Failure 1. Check if speaker cables are connected properly. 2. Make sure all the drivers are Board-level Check the following parts for cold solder or one of the following parts on the installed properly.
6.11 LAN Failure An error occurs when a LAN device is installed. LAN Failure Check the following parts for cold solder or one of the following 1.Check if the driver is installed properly. parts on the mother-board may be defective, use an oscilloscope 2.Check if the notebook connect with the to check the following signal or replace the parts one at a time and LAN properly.
6.12 Card Reader Slot Failure An error occurs when a card device is installed. Card Reader Slot Failure Check the following parts for cold solder or one of the following 1. Check if the card device is Board-level parts on the mother-board may be defective, use an oscilloscope installed properly.
6.13 Mini Express (Wireless) Socket Failure An error occurs when a wireless card device is installed. Mini Express (Wireless) Socket Failure Board-level Troubleshooting 1. Check if the wireless card device is installed properly. 2. Confirm wireless driver is installed ok. Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and...
6.14 Express Card Socket Failure An error occurs when a express card device is installed. Express Card Socket Failure Board-level Troubleshooting 1. Check if the express card device is installed properly. 2. Confirm express card driver is installed ok. Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement.
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