Getac 9270D Service Manual page 127

4.20 Dual Channel NAND Interface –Table 2
Name
NV_WR#[1:0]
/NV_RE#[1:0]
NV_CK[1:0]/
NV_WE[1:0]#
NV_RB#
NV_RCOMP
NOTE: Asynchronous Mode is included only for compliance to ONFi* 2.0. The Ibex Peak DC NAND
I/F solutions will only support in source synchronous mode.
Type
Source Synchronous Mode:
Write Read[1:0]# Indicates owner of the NV_DQ / NV_IO
and NV_DQS signals.
'1', NV_DQ / NV_IO and NV_DQS are driven by IBX
NAND Controller.
O
'0', NV_DQ / NV_IO and NV_DQS are driven by the NAND
device.
Asynchronous Mode:
Read Enable [1:0]#:Controls when NAND device will drive
input data on the NV_IO bus during read operations
Clock or Write Enable #:
Source Synchronous Interface: Provides the clock for the
source synchronous interface. The clock is free-running when
any Chip Enable NV_CE[3:0]# is asserted.
O
Asynchronous Interface:
Write Enable #: The active low signal indicates command,
address or data are driven valid by the PCH NAND controller
on the NV_IO bus.
Ready/Busy #: Indicates the status of the NAND device.
Ready/ Busy# signals from multiple NAND devices must be
I
wired-OR together to provide a single Ready/Busy# input to
NAND controller.
NAND Buffer Impedance Compensation: This pin is
I/O connected to an external precision resistor (TBD) for
impedance compensation of the NAND buffer drivers.
Description