Getac 9270D Service Manual page 123

4.16 Controller Link Signals
Name
CL_RST1#
(Mobile Only) /
TP20 (Desktop
Only)
CL_CLK1
(Mobile Only) /
TP18 (Desktop
Only)
CL_DATA1
(Mobile Only) /
TP19 (Desktop
Only)
4.1.17 Serial Peripheral Interface (SPI) Signals
Name
SPI_CS0#
SPI_CS1#
SPI_MISO
SPI_MOSI
SPI_CLK
Type
Controller Link Reset 1: Controller Link reset that connects
O to a Wireless LAN Device supporting Intel® Active
Management Technology.
Controller Link Clock 1: bi-directional clock that connects to
I/O a Wireless LAN Device supporting Intel® Active Management
Technology.
Controller Link Data 1: bi-directional data that connects to a
I/O Wireless LAN Device supporting Intel® Active Management
Technology.
Type
O SPI Chip Select 0: Used as the SPI bus request signal.
O SPI Chip Select 1: Used as the SPI bus request signal.
I SPI Master IN Slave OUT: Data input pin for Ibex Peak.
SPI Master OUT Slave IN: Data output pin for Ibex Peak.
NOTE: This signal is sampled as a functional strap. See
O
Section 4.30 for more details.There is a weak integrated pull-
down resistor on this pin.
SPI Clock: SPI clock signal, during idle the bus owner will
O
drive the clock signal low. 17.86 MHz and 31.25.
Description
Description