Getac 9270D Service Manual page 117

4.10 Processor Interface Signals
Name
RCIN#
A20GATE
PROCPWRGD
4.1.11 SM Bus Interface Signals
Name
SMBDATA
SMBCLK
SMBALERT# /
GPIO11
Type
Keyboard Controller Reset CPU: The keyboard controller
can generate INIT# to the processor. This saves the external
OR gate with the PCH's other sources of INIT#. When the
I PCH detects the assertion of this signal, INIT# is generated for
16 PCI clocks.
NOTE: The PCH will ignore RCIN# assertion during
transitions to the S3, S4, and S5 states.
A20 Gate: A20GATE is from the keyboard controller. The
signal acts as an alternative method to force the A20M# signal
I
active. It saves the external OR gate needed with various other
copyists.
Processor Power Good: This signal should be connected to
O the processor's VCCPWRGOOD_1 and VCCPWRGOOD_0
input to indicate when the processor power is valid.
Type
I/OD SMBus Data: External pull-up resistor is required.
I/OD SMBus Clock: External pull-up resistor is required.
SMBus Alert: This signal is used to wake the system or
I generate SMI#.
This signal may be used as GPIO11
Description
Description