Getac 9270D Service Manual page 125

4.19 JTAG Signals
Name
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
TRST#
NOTE: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE Std. 1149.1-2001)
Type
Test Clock Input (TCK): The test clock input provides the
I/O
clock for the JTAG test logic.
Test Mode Select (TMS): The signal is decoded by the Test
I/O
Access Port (TAP) controller to control test operations.
Test Data Input (TDI): Serial test instructions and data are
I/O
received by the test logic at TDI.
Test Data Output (TDO): TDO is the serial output for test
I/O instructions and data from the test logic defined in this
standard.
Test Reset (RST): RST is an active low asynchronous signal
that can reset the Test Access Port (TAP) controller.
I/O
Note: The RST signal is optional per the IEEE 1149.1
specification, and is not functional for Boundary Scan Testing
Description