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3.3.2
LVDS Connector
LVDS connector
CN4
Pin
Signal
Pin
Signal
1
GND
2
GND
3
LVDS_B_TX3+
4
LVDS_A_TX3+
5
LVDS_B_TX3-
6
LVDS_A_TX3-
7
LVDS_B_TX2+
8
LVDS_A_TX2+
9
LVDS_B_TX2-
10
LVDS_A_TX2-
11
LVDS_B_TX1+
12
LVDS_A_TX1+
13
LVDS_B_TX1-
14
LVDS_A_TX1-
15
LVDS_B_TX0+
16
LVDS_A_TX0+
17
LVDS_B_TX0-
18
LVDS_A_TX0-
19
GND
20
GND
21
LVDS_B_CLK+
22
LVDS_A_CLK+
23
LVDS_B_CLK-
24
LVDS_A_CLK-
25
GND
26
GND
27
LVDS_I2C_CLK
28
BKLT_EN
29
LVDS_I2C_DATA
30
BKLT_PWM
31
+3.3V_RUN
32
PVCC_EN
33
LCD_PWR
34
BKLT_PWR
35
LCD_PWR
36
BKLT_PWR
37
LCD_PWR
38
BKLT_PWR
39
GND
40
GND
41
GND
42
GND
43
GND
44
GND
45
TOUCH_RST#
46
TOUCH_SCL
47
TOUCH_INT#
48
TOUCH_SDA
49
+3.3V_RUN
50
GND
SBC-C41-pITX
SBC-C41-pITX User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author: A.R./S.B. - Reviewed by M.B. Copyright © 2021 SECO S.p.A.
SBC-C41-pITX can be interfaced to LCD displays using its LVDS interface, which
allows connecting 18 or 24 bit, single or dual channel displays. This interface is
implemented using an eDP to LVDS bridge (NXP PTN3460), which allow the
implementation of a Dual Channel LVDS, with a maximum supported resolution of
1920x1200 @ 60Hx (dual channel mode). Such an interface is derived from
Processor's eDP Interface.
For the connection, a connector type HR A1014WA-S-2x25P or equivalent (2 x 25p,
male, straight, P1, low profile, polarised) is provided.
Mating connector: HR A1014H-2X25P with HR A1014-T female crimp terminals.
Alternative mating connector, MOLEX 501189-5010 with crimp terminals series 501334.
On the same connectors, are also implemented signals for direct driving of display's backlight: voltages
(LCD_PWR and BKLT_PWR) and control signals (LCD enable signal, PVCC_EN, Backlight enable signal,
BKLT_EN, and Backlight Brightness Control signal, BKLT_PWM).
There are also the signals necessary for driving I2C touchscreens (I2C signals, reset and interrupt request
signals).
When building a cable for connection of LVDS displays, please take care of twist as tight as possible differential
pairs' signal wires, in order to reduce EMI interferences. Shielded cables are also recommended.
Here following the signals related to LVDS management:
LVDS_A_TX0+/ LVDS_A_TX0-: LVDS Channel A differential data pair #0.
LVDS_A_TX1+/ LVDS_A_TX1-: LVDS Channel A differential data pair #1.
LVDS_A_TX2+/ LVDS_A_TX2-: LVDS Channel A differential data pair #2.
LVDS_A_TX3+/ LVDS_A_TX3-: LVDS Channel A differential data pair #3.
LVDS_A_CLK+/LVDS_A_CLK-: LVDS Channel A differential Clock.
LVDS_B_TX0+/ LVDS_B_TX0-: LVDS Channel B differential data pair #0.
LVDS_B_TX1+/ LVDS_B_TX1-: LVDS Channel B differential data pair #1.
LVDS_B_TX2+/ LVDS_B_TX2-: LVDS Channel B differential data pair #2.
LVDS_B_TX3+/ LVDS_B_TX3-: LVDS Channel B differential data pair #3.
26
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