Seco SBC-C41-pITX User Manual page 52

LFP V-Sync Polarity
LFP H-Sync Polarity
LVDS Advanced Options
4.3.16.1 LVDS Advanced options submenu
Menu Item
Spreading Depth
Output Swing
T3 Timing
T4 Timing
T12 Timing
T2 Delay
T5 Delay
P/N Pairs Swapping
Pairs Order Swapping
LVDS BUS Swapping
Firmware PLL
SBC-C41-pITX
SBC-C41-pITX User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author: A.R./S.B. - Reviewed by M.B. Copyright © 2021 SECO S.p.A.
Negative / Positive Vertical Sync Polarity: Default is Negative (Active Low)
Negative / Positive Horizontal Sync Polarity: Default is Negative (Active Low)
See Submenu LVDS Advanced Options Configurations
Options Description
No Spreading / 0.5% /
1.0% / 1.5% / 2.0% / Sets percentage of bandwidth of LVDS clock frequency for spreading spectrum
2.5%
150 mV / 200 mV / 250
mV / 300 mV / 350 mV / Sets the LVDS differential output swing
400 mV / 450 mV
Minimum T3 timing of panel power sequence to enforce (expressed in units of 50ms). Default is 10
0 ÷ 255
(500ms)
0 ÷ 255 Minimum T4 timing of panel power sequence to enforce (expressed in units of 50ms). Default is 2 (100ms)
0 ÷ 255 Minimum T12 timing of panel power sequence to enforce (expressed in units of 50ms). Default is 20 (1s)
Enabled / Disabled When Enabled, T2 is delayed by 20ms ± 50%
Enabled / Disabled When Enabled, T5 is delayed by 20ms ± 50%
Enable or disable LVDS Differential pairs swapping (Positive  Negative)
Enabled / Disabled
Enable or disable channel differential pairs order swapping (A  D, B  CLK, C  C)
Enabled / Disabled
Enable or disable Bus swapping (Odd  Even)
Enabled / Disabled
0: +/- 1.56%
1: +/- 3.12%
2: +/- 6.25%
3: +/- 12.5% Set Firmware PLL range
4: +/- 25%
5: +/- 50%
6: +/- 100%
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