Lvds + Backlight Connector - Seco SBC-C20 User Manual

LVDS + backlight connector

LVDS + backlight connector
Pin Signal Pin
2 +12V BKL2 1
4 VCC BKL SW 3
6 VCC BKL SW 5
8 GND 7
10 LVDS0_TX0+ 9
12 GND 11
14 LVDS0_TX1+ 13
16 GND 15
18 LVDS0_TX2+ 17
20 GND 19
22 LVDS0_TX3+ 21
24 GND 23
26 LVDS0_CLK+ 25
28 DISPLAY_BKL_CTRL 27
30 LVDS_PANEL_ON 29
32 GND 31
34 LVDS1_TX0+ 33
36 GND 35
38 LVDS1_TX1+ 37
40 GND 39
42 LVDS1_TX2+ 41
44 GND 43
46 LVDS1_TX3+ 45
48 GND 47
50 LVDS1_CLK+ 49
SBC-C20
SBC-C20 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R. - Reviewed by C.M. -Copyright © 2020 SECO S.p.A.
SBC-C20 board can be interfaced to LCD displays using its LVDS
CN18
interface, which allows the connection of displays with a colour depth of
18 or 24 bit, single or dual channel.
Signal
For the connection, a connector type HR A1014WV-S-2X25P or
+12V BKL1
equivalent (2 x 25p, male, straight, P1, low profile, polarized) is provided,
VCC_LCD_SW
with the pin-out shown in the table below.
DISPLAY_ANA_BKL
Mating connector: HR A1014H -2X25P with HR A1014-T female crimp
GND
terminals.
LVDS0_TX0-
Alternative mating connector, MOLEX 501189-5010 with crimp terminals series 501334.
GND
LVDS0_TX1-
power voltages for LCD and backlight (VCC_BKL_SW and VCC_LCD_SW) and control signals
GND
(Backlight enable signal, DISPLAY_BKL_ON, LCD enable signal, LVDS_PANEL_ON, PWM and
LVDS0_TX2-
Analog Backlight Brightness Control signal, DISPLAY_BKL_CTRL and DISPLAY_ANA_BKL).
GND
When building a cable for connection of LVDS displays, please take care of twist as tight as possible
LVDS0_TX3-
GND recommended. Here following the signals related to LVDS management:
LVDS0_CLK-
LVDS0_TX0+/LVDS0_TX0-: LVDS Channel #0 differential data pair #0.
GND
LVDS0_TX1+/LVDS0_TX1-: LVDS Channel #0 differential data pair #1.
DISPLAY_BKL_ON
LVDS0_TX2+/LVDS0_TX2-: LVDS Channel #0 differential data pair #2.
GND
LVDS0_TX3+/LVDS0_TX3-: LVDS Channel #0 differential data pair #3.
LVDS1_TX0-
LVDS0_CLK+/LVDS0_CLK-: LVDS Channel #0 differential Clock.
GND
LVDS1_TX0+/LVDS1_TX0-: LVDS Channel #1 differential data pair #0.
LVDS1_TX1-
LVDS1_TX1+/LVDS1_TX1-: LVDS Channel #1 differential data pair #1.
GND
LVDS1_TX2+/LVDS1_TX2-: LVDS Channel #1 differential data pair #2.
LVDS1_TX2-
LVDS1_TX3+/LVDS1_TX3-: LVDS Channel #1 differential data pair #3.
GND
LVDS1_CLK+/LVDS1_CLK-: LVDS Channel #1 differential Clock.
LVDS1_TX3-
12V_BKL1, 12V_BKLT2: 12V power rails, directly connected to Input Voltage VIN_SYS, fuse
GND
protected (max 1.85A per rail).
LVDS1_CLK+
VCC_BKL_SW: SW enabled Backlight power rail. Please check par. 3.3.23
terferences. Shielded cables are also
24