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3.3.8
M.2 2230 Socket 1 Key E Connectivity Slot
M.2 Connectivity Slot (Socket 1 Key E type 2230) - CN15
Pin
Signal
1
GND
3
USB_P3+
5
USB_P3-
7
GND
9
---
11
---
13
---
15
---
17
---
19
---
21
---
23
---
33
GND
35
PCIe0_Tx+
37
PCIe0_Tx-
39
GND
41
PCIe0_Rx+
43
PCIe0_Rx-
45
GND
47
PCIe0_CLK+
49
PCIe0_CLK-
51
GND
53
CLK_REQ0#
55
PCIe_WAKE#
57
GND
SBC-C41-pITX
SBC-C41-pITX User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author: A.R./S.B. - Reviewed by M.B. Copyright © 2021 SECO S.p.A.
Pin
Signal
2
+3.3V_ALW
4
+3.3V_ALW
6
---
8
---
10
---
12
---
14
---
16
---
18
GND
20
---
22
---
32
---
34
---
36
---
38
---
40
---
42
---
44
---
46
---
48
---
50
SUS_CLK
52
PLT_RST#
54
KEYE_W_DISABLE2#
56
KEYE_W_DISABLE1#
58
---
It is possible to increase the connectivity of the SBC-C41 board by using M.2 Socket 1 Key
E connectivity slot.
The connector used for the M.2 Connectivity slot is CN15,
which is a standard 75 pin M.2 Key E connector, type
LOTES p/n APCI0076-P001A, H=4.2mm, with the pinout
shown in the table on the left.
On the SBC-C41 board there is also a Threaded Spacer
which allows the placement of M.2 Socket 1 Key E
connectivity modules in 2230 size.
59
---
61
---
63
GND
65
---
67
---
69
GND
71
---
73
---
75
GND
Signal Description
USB_P3+ / USB_P3-: USB Port #3 differential pair; it is managed by
controller.
PCIe0_Tx+/PCIe0_Tx-: PCI Express lane #0, Transmitting Output Differential pair
PCIe0_Rx+/PCIe0_Rx-: PCI Express lane #0, Receiving Input Differential pair
PCIe0_CLK+/ PCIe0_CLK-: PCI Express Reference Clock for lane #0, Differential Pair
PCIe_WAKE#: Board's Wake Input, it must be externally driven by the module inserted in
the slot when it requires waking up the system.
60
---
62
---
64
---
66
---
68
---
70
---
72
+3.3V_ALW
74
+3.3V_ALW
xHCI
34
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