Alinx ZYNQ7000 FPGA User Manual page 41

The Ethernet chip uses Micrel's KSZ9031RNX Ethernet PHY chip to
provide network communication services to users. The Ethernet PHY chip on
the PS side is connected to the GPIO interface of the PSNK501 of the PS side
of ZYNQ. The Ethernet PHY chip on the PL side is connected to the IO of the
BANK35. The KSZ9031RNX chip supports 10/100/1000 Mbps network
transmission rate and communicates with the MAC layer of the Zynq7000
system through the RGMII interface. KSZ9031RNX supports MDI/MDX
adaptation, various speed adaptation, Master/Slave adaptation, and supports
MDIO bus for PHY register management.
The KSZ9031RNX power-on will detect the level status of some specific
IOs to determine their working mode. Table 3-1-1 describes the default setup
information after the GPHY chip is powered up.。
Configuration Pin
PHYAD[2:0]
CLK125_EN
LED_MODE
MODE0~MODE3
When the network is connected to Gigabit Ethernet, the data
transmission of ZYNQ and PHY chip KSZ9031RNX is communicated through
the RGMII bus, the transmission clock is 125Mhz, and the data is sampled on
the rising edge and falling samples of the clock.
When the network is connected to 100M Ethernet, the data transmission of
ZYNQ and PHY chip KSZ9031RNX is communicated through RMII bus, and
the transmission clock is 25Mhz. Data is sampled on the rising edge and falling
samples of the clock. Figure 3-3-1 detailed the connection of the ZYNQ PS end
1 way Ethernet PHY chip, and Figure 3-3-2 detailed the connection of the 1
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ZYNQ FPGA Development Board AX7Z100 User Manual
Instructions
MDIO/MDC Mode PHY Address
Enable 125Mhz clock output
selection
LED light mode configuration
Link adaptation and full duplex
configuration
Table 3-1-1: PHY chip default configuration value
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Configuration value
PHY Address 011
Enable
Single LED light mode
10/100/1000 adaptive, compatible
with full-duplex, half-duplex