Alinx ZYNQ7000 FPGA User Manual page 25

PL Clock pin assignment:
GTX reference clock
The FPGA core board AC7Z100 provides a 125Mhz reference clock for
the GTX transceiver. The reference clock is connected to the reference clock
input REFCLK1P/REFCLK1N of the BANK111. The schematic diagram of the
clock source is shown in Figure 2-6-4.
Figure 2-6-5: Programmable Clock Source on the AX7Z100 FPGA Core Board
GTX clock source ZYNQ pin assignment:：
BANK111_CLK1_P
BANK111_CLK1_N
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ZYNQ FPGA Development Board AX7Z100 User Manual
Signal Name
SYS_CLK_P
SYS_CLK_N
Figure 2-6-4: GTX Clock Source
Signal Name
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ZYNQ Pin
F9
E8
ZYNQ Pin
AC8
AC7