Alinx ZYNQ7000 FPGA User Manual page 18

PS_DDR3_WE
PS_DDR3_ODT
PS_DDR3_RESET
PS_DDR3_CLK0_P
PS_DDR3_CLK0_N
PS_DDR3_CKE
PL side DDR3 DRAM pin assignment:
Signal Name
PL_DDR3_DQS0_P
PL_DDR3_DQS0_N
PL_DDR3_DQS1_P
PL_DDR3_DQS1_N
PL_DDR3_DQS2_P
PL_DDR3_DQS2_N
PL_DDR3_DQS3_P
PL_DDR3_DQS4_N
PL_DDR3_D0
PL_DDR3_D1
PL_DDR3_D2
PL_DDR3_D3
PL_DDR3_D4
PL_DDR3_D5
PL_DDR3_D6
PL_DDR3_D7
PL_DDR3_D8
PL_DDR3_D9
PL_DDR3_D10
PL_DDR3_D11
PL_DDR3_D12
PL_DDR3_D13
PL_DDR3_D14
PL_DDR3_D15
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ZYNQ FPGA Development Board AX7Z100 User Manual
PS_DDR_WE_B_502
PS_DDR_ODT_502
PS_DDR_DRST_B_502
PS_DDR_CKP_502
PS_DDR_CKN_502
PS_DDR_CKE_502
ZYNQ Pin Name
IO_L3P_T0_DQS_33
IO_L3N_T0_DQS_33
IO_L9P_T1_DQS_33
IO_L9N_T1_DQS_33
IO_L15P_T2_DQS_33
IO_L15N_T2_DQS_33
IO_L21P_T3_DQS_33
IO_L21N_T3_DQS_33
IO_L5N_T0_33
IO_L1N_T0_33
IO_L4P_T0_33
IO_L1P_T0_33
IO_L2N_T0_33
IO_L5P_T0_33
IO_L2P_T0_33
IO_L4N_T0_33
IO_L7N_T1_33
IO_L10N_T1_33
IO_L7P_T1_33
IO_L8N_T1_33
IO_L11N_T1_SRCC_33
IO_L8P_T1_33
IO_L11P_T1_SRCC_33
IO_L10P_T1_33
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N23
L23
F25
K25
J25
M22
ZYNQ Pin Number
K3
K2
J1
H1
E6
D5
A5
A4
J3
L2
J4
L3
K1
K6
J5
K5
H4
G1
H6
F2
H2
G4
G6
H3