Part 2.3: Ddr3 Dram - Alinx ZYNQ7000 FPGA User Manual

Figure 2-2-3: The XC7Z100 chip used on the Core Board

Part 2.3: DDR3 DRAM

The FPGA core board AC7Z100 is equipped with four Micron 512MB
DDR3 chips,
MT41K256M16HA-125), in which Two DDR3s are mounted on the PS and PL
sides respectively. Two DDR3 SDRAMs form a 32-bit bus width. The PS-side
DDR3 SDRAM has a maximum operating speed of 533MHz (data rate
1066Mbps), and two DDR3 memory systems are directly connected to the
memory interface of the BANK 502 of the ZYNQ Processing System (PS). The
PL-side DDR3 SDRAM has a maximum operating speed of 800MHz (data rate
1600Mbps), and two DDR3 memory systems are connected to the BANK33
and BANK34 interfaces of the FPGA. The specific configuration of DDR3
SDRAM is shown in Table 2-3-1.
Bit Number
U4,U5,U7,U8
The hardware design of DDR3 requires strict consideration of signal
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ZYNQ FPGA Development Board AX7Z100 User Manual
model MT41J256M16HA-125
Chip Model
MT41J256M16HA-125
Table 2-3-1: DDR3 SDRAM Configuration
Amazon Store: https://www.amazon.com/alinx
(compatible
Capacity Factory
256M x 16bit
with
Micron