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16.6.3 OnCE Status Register (OSR)
The OnCE status register (OSR) is a 16-bit register used to indicate the reason(s)
that debug mode was entered and the current operating mode of the CPU. These sta-
tus bits are read only.
OSR — OnCE Status Register
15
14
13
12
R
0
0
0
0
W
RESET:
HDRO — Hardware Debug Request Occurrence
This read-only status bit is set when the processor enters debug mode as a result of
a hardware debug request from the IDR signal or the DE pin. This bit is cleared on
test logic reset or when debug mode is exited with the GO and EX bits set.
DRO — Debug Request Occurrence
This read-only status bit is set when the processor enters debug mode and the debug
request (DR) control bit in the OnCE control register is set. This bit is cleared on test
logic reset or when debug mode is exited with the GO and EX bits set.
MBO — Memory Breakpoint Occurrence
This read-only status bit is set when a memory breakpoint request has been issued to
the CPU via the BRKRQ input and the CPU enters debug mode. In some situations
involving breakpoint requests on instruction prefetches, the CPU may discard the
request along with the prefetch. In this case, this bit may become set due to the CPU
entering debug mode for another reason. This bit is cleared on test logic reset or
when debug mode is exited with the GO and EX bits set.
SWO — Software Debug Occurrence
This read-only status bit is set when the processor enters debug mode of operation
as a result of the execution of the bkpt instruction. This bit is cleared on test logic
reset or when debug mode is exited with the GO and EX bits set.
TO — Trace Count Occurrence
This read-only status bit is set when the trace counter reaches zero with the trace
mode enabled and the CPU enters debug mode. This bit is cleared on test logic reset
or when debug mode is exited with the GO and EX bits set.
FRZO — FIFO Freeze Occurrence
This read-only status bit is set when a FIFO freeze occurs. This bit is cleared on test
logic reset or when debug mode is exited with the GO and EX bits set.
SQB — Sequential Breakpoint B Arm Occurrence
This read-only status bit is set when sequential operation is enabled and a memory
breakpoint B event has occurred to enable trace counter operation. This bit is cleared
on test logic reset or when debug mode is exited with the GO and EX bits set.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
11
10
9
8
0
0
HDRO DRO
0
0
Figure 16-6 OnCE Status Register
OnCE™ DEBUG MODULE
For More Information On This Product,
Go to: www.freescale.com
7
6
5
4
MBO
SWO
TO
FRZO
0
0
0
0
3
2
1
0
SQB
SQA
PM
0
0
0
0
MOTOROLA
16-11
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