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9.5.1 Watchdog Timing Specifications
The watchdog timer provides time-out periods from 0.5 seconds up to 32 seconds
with a time resolution of 0.5 seconds. It uses a 2-Hz clock derived from a
LOW_REFCLK prescaler (divide by 16384) to achieve the resolution of 0.5 seconds.
The output of the prescaler circuitry is connected to the input of a 6-bit counter, result-
ing in a range of 0.5 to 32 seconds. The time-out period is determined by writing the
watchdog time-out field (WT) in the watchdog control register. Figure 9-9 shows a
block diagram of the watchdog timer.
The internal count registers are clocked using the 2-Hz reference. In
order to read and write these registers accurately via the CPU core
(which runs from the CPU_CLK), clock synchronization logic is required
internal to the watchdog. This logic requires that the CPU clock
frequency be greater than or equal to the LOW_REFCLK clock from
which the counter clocks are derived.
9.5.2 Watchdog Timer after Reset
The watchdog is disabled by default after reset. Once enabled by software, it cannot
be disabled. The watchdog enable bit (WDE) is located in the watchdog control regis-
ter. At reset, the watchdog control register and watchdog service register are initial-
ized to zero.
9.5.3 Watchdog Timer Service Operation
A service sequence must be executed periodically to keep the watchdog from timing
out and causing a reset. The service routine is based on writing to the watchdog ser-
vice register. See 9.5.8.2 Watchdog Service Register (WSR).
9.5.4 Watchdog Timer in Wait Mode
In wait mode, all peripheral clocks run normally. The watchdog is not affected.
9.5.5 Watchdog Timer in Doze Mode
In doze mode, the watchdog may either continue to run or be halted. If the WDZE
(watchdog doze enable) bit is set in the watchdog control register (WCR), the watch-
dog is halted. When doze mode is exited, the watchdog operation reverts to what it
was prior to entering doze mode.
9.5.6 Watchdog Timer in Stop Mode
In stop mode, the watchdog may either continue to run or be halted. If the WSTP
(watchdog stop enable) bit is set in the watchdog control register (WCR), the watch-
dog is halted. When stop mode is exited, the watchdog operation reverts to what it
was prior to entering stop mode.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
NOTE
TIMER/RESET MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
9-9
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