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In the MMC2001, interrupt requests to the CPU are always treated as autovectored.
The interrupt controller accomplishes this by asserting the CPU AVEC input along
with the appropriate interrupt request. An interrupt handler can read the NIPND or
FIPND register and then vector based on the value received.
The INTSRC register inputs at bit positions [0:2] are reserved for software generation
of interrupts and are always forced to a one. By enabling interrupts for these bit posi-
tions, software can force an interrupt request.
The interrupt requests are prioritized in the following sequence:
1. Fast interrupt requests
2. Normal interrupt requests
The two interrupt lines INT and FINT are mutually exclusive. If FINT is asserted while
INT is already asserted, INT is automatically negated.
10.2 Interrupt Controller Programming Model
Control and status registers for the interrupt controller begin at address 0x40002000.
Table 10-1 Interrupt Controller Address Map
Address
10000000
10000004
10000008
1000000C
10000010
10.2.1 Interrupt Source Register (INTSRC)
Access the 32-bit interrupt source register with 32-bit loads only.
INTSRC — Interrupt Source Register
31
30
29
28
IN31
IN30
IN29
IN28
RESET:
15
14
13
12
IN15
IN14
IN13
IN12
RESET:
MOTOROLA
10-2
Freescale Semiconductor, Inc.
Use
Interrupt Source Register (INTSRC)
Normal Interrupt Enable Register (NIER)
Fast Interrupt Enable Register (FIER)
Normal Interrupt Pending Register (NIPND)
Fast Interrupt Pending Register (FIPND)
27
26
25
24
IN27
IN26
IN25
IN24
11
10
9
8
IN11
IN10
IN9
IN8
Figure 10-1 Interrupt Source Register
INTERRUPT CONTROLLER
For More Information On This Product,
Go to: www.freescale.com
Supervisor Only
Supervisor Only
Supervisor Only
Supervisor Only
Supervisor Only
23
22
21
20
IN23
IN22
IN21
IN20
7
6
5
4
IN7
IN6
IN5
IN4
Access
10000000
19
18
17
16
IN19
IN18
IN17
IN16
3
2
1
0
IN3
1
1
1
MMC2001
REFERENCE MANUAL
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