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U0TX — UART0 Transmitter Register
U1TX — UART1 Transmitter Register
15
14
13
12
0
0
0
0
RESET:
0
0
0
0
*n = 0, 1, . . ., 15
X = Undefined
TX DATA — Transmit Data
These write-only bits are the parallel transmit data inputs. In 7-bit mode, D7 is
ignored. In 8-bit mode, all bits are used. Data is transmitted LSB first. A new charac-
ter is transmitted when these bits are written. These bits must be written only while
TRDY is high to ensure that corrupted data is not sent.
11.4.3 UART Control Register 1 (UCR1)
UART control register 1 is a read/write register. This register enables the UART and
the transmit and receive blocks. It controls the Tx and Rx FIFO levels and enables the
TRDY and RRDY interrupts.
U0CR1 — UART0 Control Register 1
U1CR1 — UART1 Control Register 1
15
14
13
12
R
TRDY-
TxFL
TXEN
EN
W
RESET:
0
0
0
0
TxFL — Transmitter FIFO Interrupt Trigger Level
These bits control the operation of the interrupt generated by the transmitter. A
maskable interrupt is generated whenever the data level in the TX FIFO drops below
the selected threshold. The bits are encoded as follows:
Value
00
01
10
11
At reset, these bits are cleared to zero.
MMC2001
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
REFERENCE MANUAL
Freescale Semiconductor, Inc.
11
10
9
8
0
0
0
0
0
0
0
0
Figure 11-3 UART Transmitter Register
11
10
9
8
RRDY
RxFL
RXEN IREN
EN
0
0
0
0
Figure 11-4 UART Control Register 1
Table 11-2 TxFL Field Settings
Interrupt if TX FIFO has a slot for one or more character
Interrupt if TX FIFO has a slot for four or more characters
Interrupt if TX FIFO has a slot for eight or more characters
Interrupt if TX FIFO has a slot for fourteen or more characters
For More Information On This Product,
Go to: www.freescale.com
7
6
5
4
TX DATA
X
X
X
X
7
6
5
4
0
RTSD
SND-
EN
BRK
0
0
0
Meaning
10009040
1000A040
3
2
1
0
X
X
X
X
10009080
1000A080
3
2
1
0
0
0
UART
DOZE
EN
0
0
MOTOROLA
11-9
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