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FPx — Fast Interrupt Pending Flag x
This bit indicates a pending fast interrupt request from the corresponding interrupt
source.
0 = No request
1 = Interrupt request pending
When a fast interrupt enable flag is set and the corresponding interrupt line is
asserted, the interrupt controller will assert a fast interrupt request (FINT CPU input).
The fast interrupt pending flags reflect the interrupt input lines which are currently
enabled to generate a fast interrupt and are asserted.
C.3 Timer/Reset Programming Model
Table C-3 shows the timer/reset module address map.
Table C-3 Timer/Reset Module Address Map
Address
10001000
10001004
10001008
1000100C
10001010
10001014
10001018
1000101C
10001020
10001024
10001028
1000102C
1000102E
to
10001FFF
10002000
to
10002FFF
C.3.1 Reset Source/Chip Configuration Register (RSCR)
This status and control register gives the state of the reset sources and serves to
control the CLKOUT pin. Writes to this register clear any previously set status bits.
Access this register with 32-bit loads and stores only.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Use
Reset Source/Chip Configuration Register (RSCR)
Time-of-Day Control/Status Register (TODCSR)
Time-of-Day Seconds Register (TODSR)
Time-of-Day Fraction Register (TODFR)
Time-of-Day Seconds Alarm Register (TODSAR)
Time-of-Day Fraction Alarm Register (TODFAR)
Reserved
Watchdog Control Register (WCR)
Watchdog Service Register (WSR)
Interval Timer Control/Status Register (ITCSR)
PIT Data Register (ITDR)
PIT Alternate Data Register (ITADR)
Reserved
Not Used (Access causes transfer error)
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
Access
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Not Applicable
MOTOROLA
C-5
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