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TXMPTY — Transmitter Empty
When set, this bit indicates that the transmit FIFO and the transmit shift register are
both empty. This bit is automatically cleared when a write to the TX FIFO is per-
formed.
0 = TX FIFO or shifter are not both empty
1 = TX FIFO and shifter are both empty
At reset, this bit is set to one.
RTSS — RTS Pin Status
This bit indicates the current status of the RTS pin. A "snapshot" of the pin is taken
immediately before this bit is presented to the data bus. While IRTS is asserted, this
bit can be used as a general-purpose input.
0 = RTS pin is high (inactive)
1 = RTS pin is low (active)
This bit follows the logic value connected to the RTS pin.
TRDY — Transmitter Ready Interrupt Flag
When set, this bit indicates that the TX FIFO has emptied below its target threshold
and needs data. This bit is automatically cleared when the data level in the TX FIFO
goes beyond the set threshold level.
0 = Transmitter does not need data
1 = Transmitter needs data (interrupt posted)
At reset, this bit is set to one.
RRDY — Receiver Ready Interrupt Flag
When set, this bit indicates that the receive FIFO data level is above the threshold
level specified by the RxFL field, and a maskable interrupt is generated. Refer to the
RxFL bit description for setting the threshold level. In conjunction with the CHARRDY
bit, host software can continue to read the RX FIFO in an interrupt service routine
until the RX FIFO is empty. This bit is automatically cleared when the data level in the
RX FIFO goes below the set threshold level.
0 = No character ready (no interrupt posted)
1 = Character(s) ready (interrupt posted)
At reset, this bit is cleared to zero.
RTSD — RTS Delta
When set, this bit indicates that the RTS pin changed state. It generates a maskable
interrupt. In STOP mode, RTS assertion sets this bit to wake the CPU. The current
state of the RTS pin is available in the RTSS bit. The RTSD interrupt is cleared by
writing a one to this bit.
0 = RTS pin did not change state since last cleared
1 = RTS pin changed state
At reset, this bit is cleared to zero.
C.9.7 UART Test Register (UTSR)
The UART test register is a read/write register. Unimplemented bits always return
zero when read. This register contains miscellaneous bits to control test features of
the UART block.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
C-43
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