External Bus Timing Diagrams; Show Cycle Enable Field Settings - Motorola M-CORE MMC2001 Series Reference Manual

Table 7-6 Show Cycle Enable Field Settings
Value
00
01
10
11

7.8 External Bus Timing Diagrams

The following timing diagrams show the timing of accesses to memory or peripherals.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Show cycles disabled. The external address bus is driven with the last valid
external address, and the data bus values are held by bus keepers.
Show cycles enabled. Internal termination to the CPU during idle cycles caused
by EDC or CSA being set follows normal operation as shown in Figure 7-11,
Figure 7-12, and Figure 7-13. This means that internal transfers that occur dur-
ing EDC/CSA idle cycles will not be visible externally.
Show cycles enabled. Internal termination to the CPU during idle cycles caused
by EDC or CSA being set is delayed by one clock. This ensures that all internal
transfers can be externally monitored, at the expense of performance.
Reserved
EXTERNAL INTERFACE MODULE
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Meaning
MOTOROLA
7-13