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C.10.10 Instruction Register (IR)
The instruction register (IR) provides a mechanism for controlling the debug session
by forcing in selected instructions and then causing them to be executed in a con-
trolled manner by the debug control block.
C.10.11 Control State Register (CTL)
The control state register (CTL) is used to set control values when debug mode is
exited. On scan-in, this register is used to control specific aspects of the CPU. Certain
bits reflect internal processor status and should be restored to their original values.
The CTL is a 16-bit latch that stores the value of certain internal CPU state variables
before debug mode is entered. This register is affected by the operations performed
during the debug session and should be restored by the external command controller
when returning to normal mode. In addition to saved internal state variables, the bits
are used by emulation firmware to control the debug process.
Set reserved bits to ones.
CTL — Control State Register
15
14
13
12
R
Reserved
W
RESET:
FFY — Feed Forward Y Operand
This control bit is used to force the content of the WBBR to be used as the Y operand
value of the first instruction to be executed following an update of the CPUSCR. This
gives the debug firmware the capability of updating processor registers by initializing
the WBBR with the desired value, setting the FFY bit, and executing a mov instruc-
tion to the desired register.
FDB — Force PSR Debug Mode
A logical OR of this control bit with the PSR(DB) bit determines whether the proces-
sor is operating in debug enable mode or not. The processor can be placed in debug
enable mode by setting this bit regardless of the state of the PSR(DB) bit. In debug
enable mode, execution of the bkpt instruction as well as recognition of the BRKRQ
input cause the processor to enter debug mode, as if the DBGRQ input had been
asserted.
SZ — Prefetch Size
This control field is used to drive the CPU SIZ[1:0] outputs on the first instruction
prefetch caused by issuing a OnCE command with the GO bit set and not ignored. It
should be set to indicate a 16-bit size, i.e., 0b10. This field should be restored to its
original value after a debug session is completed, i.e., when a OnCE command is
issued with the GO and EX bits set and not ignored.
MOTOROLA
C-52
Freescale Semiconductor, Inc.
11
10
9
8
FFY
0
Figure C-49 Control State Register
PROGRAMMING REFERENCE
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7
6
5
4
FDB
SZ
0
0
0
0
3
2
1
0
TC
Reserved
0
0
MMC2001
REFERENCE MANUAL
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