Pwm Programming Model; Pwm Prescaler - Motorola M-CORE MMC2001 Series Reference Manual

The width and period registers are double-buffered so that a new value can be loaded
for the next cycle without disturbing the current cycle. At the beginning of each period,
the contents of the buffer registers are loaded into the comparator for the next cycle.
Sampled audio can be recreated by feeding a new sample value into the width regis-
ter on each interrupt.
A single shared prescaler provides operating flexibility. Figure 15-3 describes its
functionality. The prescaler contains a variable divider that can divide the incoming
clock by certain values between four and 65536.
Divide Divide
By 2
By 4
Each PWM channel can independently select a prescaler tap point. In addition, each
channel provides a maskable interrupt request that can be asserted after each period
compare event.
Channels can be used as periodic interrupt sources. In this case, the output pin asso-
ciated with a channel can be used as a general-purpose I/O pin operating indepen-
dently of the timing function.

15.2 PWM Programming Model

This section describes the registers and control bits in the PWM module. All registers
reset to 0x0000 after reset.
These registers must be accessed with halfword accesses. Accesses other than half-
word in size result in undefined activity.
MOTOROLA
15-2
Freescale Semiconductor, Inc.
Divide Divide
Divide
By 2
By 4 By 4
Figure 15-3 PWM Prescaler
PULSE WIDTH MODULATOR
For More Information On This Product,
Go to: www.freescale.com
Divide
Divide
Divide
By 8
By 4
By 8
CLK SEL
REFERENCE MANUAL
CLK
SEL
MMC2001