Motorola M-CORE MMC2001 Series Reference Manual page 129

In slave mode, the ISPI operates as a traditional slave SPI; the clock becomes an
input, and the transfer is controlled entirely by the external master device.
SPI_CLK
(PHA=0, POL=0)
SPI_CLK
(PHA=0, POL=1)
SPI_CLK
(PHA=1, POL=0)
SPI_CLK
(PHA=1, POL=1)
SPI_EN
(SNS=0)
SPI_OUT
SPI_IN
Note: SPI_IN and SPI_OUT can appear on either SPI_MOSI and SPI_MISO,
depending on the mode selected by the MSTR bit.
Figure 12-2 Timing Diagram of ISPI 8-Bit Operation
The ISPI supports clocked transfers of all variations of phase and polarity by control-
ling SPI_CLK (see Figure 12-2). Under normal phase (PHA=0), data is latched with
the leading edge of SPI_CLK, and data changes with the trailing edge of SPI_CLK.
For normal phase, the leading edge is rising if POL=0, and is falling if POL=1. Under
opposite phase (PHA=1), data changes on the leading edge of SPI_CLK and is
latched on the trailing edge. For opposite phase, the leading edge is rising if POL=0
and is falling if POL=1. This flexibility allows operation with most serial peripheral
devices on the market.
12.2.1 Manual (Master) Mode
When a data exchange is needed, the user sets the SPI_EN bit in the ISPI control
register. Control values such as the number of transfer clocks, polarity, and phase are
also loaded into the ISPI control register. The transfer is initiated by writing the ISPI
Tx data register. During the transfer, data in the shift register is exchanged with data
in the peripheral. Setting the IRQ_EN bit enables the posting of an interrupt upon
completion of the transfer. The user then negates the SPI_EN register bit to complete
the operation.
For systems that need more than 16 clocks to transfer data, the SPI_EN bit can
remain set between exchanges.
MOTOROLA
12-2
Freescale Semiconductor, Inc.
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INTERVAL MODE SERIAL PERIPHERAL INTERFACE
For More Information On This Product,
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MMC2001
REFERENCE MANUAL