Pit Control/Status Register (Itcsr); Pit Control And Status Register - Motorola M-CORE MMC2001 Series Reference Manual

9.6.5 PIT Control/Status Register (ITCSR)

ITCSR — Interval Timer Control and Status Register
31 30 29 28
R 0 0 0 0
W
RESET:
15 14 13 12
R 0 0 0 0
W
RESET:
Access this register with 32-bit loads and stores only.
STOP — Stop Mode Control
This bit controls the function of the PIT in stop mode
0 = PIT function is not affected in stop mode
1 = PIT function is frozen in stop mode
DOZE — Doze Mode Control
This bit controls the function of the PIT in doze mode
0 = PIT function is not affected in doze mode
1 = PIT function is frozen in doze mode
DBG — Debug Mode Control
This bit controls the function of the PIT in debug mode
0 = PIT function is not affected in debug mode
1 = PIT function is frozen in debug mode
OVW — Counter Overwrite Enable
This bit controls what happens to the counter value when the modulus latch is written.
0 = Modulus latch is a holding register for values to be loaded into the counter
when the count expires to zero.
1 = Modulus latch is transparent. All writes to the latch will also overwrite the
counter contents.
ITIE — PIT Interrupt Enable
This bit controls the PIT interrupt function.
0 = ITIF is inhibited from reaching the CPU.
1 = ITIF is allowed to request an interrupt.
ITIF — PIT Interrupt Flag
This bit is the PIT interrupt flag. It is cleared by writing a one to this bit or by writing to
the PIT data register.
0 = No PIT interrupt is present
1 = PIT interrupt is present
MOTOROLA
9-14
Freescale Semiconductor, Inc.
27 26 25 24
0 0 0
11 10 9
0 0 0
Figure 9-16 PIT Control and Status Register
TIMER/RESET MODULE
For More Information On This Product,
Go to: www.freescale.com
23 22 21
0 0 0 0
8 7 6 5
0
STOP DOZE DBG OVW
0 0 0
10001024
20 19 18 17
0 0 0 0
4 3 2 1
ITIE ITIF RLD
0 0 0 0
MMC2001
REFERENCE MANUAL
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0
0
EN
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