Tod Seconds Register (Todsr); Tod Fraction Register (Todfr); Tod Seconds Register - Motorola M-CORE MMC2001 Series Reference Manual

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This bit controls the alarm interrupt function

0 = AIF is inhibited from reaching the CPU

1 = AIF is allowed to request an interrupt

AIF — Alarm Interrupt Flag

This read-only bit is the alarm interrupt flag. It is cleared by writing to the TOD alarm

fraction register (TODFAR).

0 = No alarm interrupt is present

1 = Alarm interrupt is present

9.4.4 TOD Seconds Register (TODSR)

The time-of-day seconds register is a 32-bit read/write register that holds the number

of elapsed seconds. It is clocked by a 1-Hz signal generated as a carry from the TOD

fraction register. When TODSR is read, the content of the fraction counter is latched

into a holding buffer to be read later. This prevents a fraction rollover between reads

of the two registers from causing incorrect data to be read. When TODSR is written,

the TODFR is cleared to all zeros. TODSR is not affected by the watchdog reset or by

a reset initiated by the external reset signal, but is undefined after a POR.

Access this register with 32-bit loads and stores only.

TODSR — Time-of-Day Seconds Register

RESET:

9.4.5 TOD Fraction Register (TODFR)

The 32-bit time-of-day fraction register holds eight bits of data that represent the

binary fraction of a second. It is clocked by the 32.768-kHz LOW_REFCLK divided by

128 (256 Hz). Reads of this register return the value latched when the TOD seconds

TODSR is read and new data is latched from the fraction counter. These eight bits are

cleared whenever the TODSR is written but are not affected by either reset pin or the

watchdog reset conditions. The fraction counter is undefined after a POR. Writes to

this register cause all eight bits to be set.

Access this register with 32-bit accesses only.

MOTOROLA

9-6

Freescale Semiconductor, Inc.