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WCR — Watchdog Control Register
31
30
29
28
R
0
0
0
0
W
RESET:
15
14
13
12
R
WT
W
RESET:
0
0
0
0
WT — Watchdog Time-Out
The six-bit WT field contains the time-out value. These bits are reloaded into the
watchdog timer when it has been serviced. After reset, write WT before enabling the
watchdog. The value in WT is loaded into the watchdog counter after running the ser-
vice routine as well as on enabling the watchdog timer.
WSTP — Watchdog Stop Enable (one-time writable)
0 = Watchdog not affected while in stop mode
1 = Watchdog disabled while in stop mode
WDE — Watchdog Enable (one-time writable)
0 = Watchdog is disabled
1 = Watchdog is enabled (once set, watchdog cannot be disabled)
WDBG — Watchdog Debug Enable (one-time writable)
0 = Watchdog not affected while in debug mode
1 = Watchdog disabled while in debug mode
WDZE — Watchdog Doze Enable (one-time writable)
0 = Watchdog not affected while in doze mode
1 = Watchdog disabled while in doze mode
C.3.8 Watchdog Service Register (WSR)
When enabled, the watchdog requires that a service sequence be written to the
watchdog service register (WSR). This register controls the clearing of the watchdog
counter to keep it from timing out and causing a reset. If this register is not written
with 0x5555 followed by 0xAAAA before the selected rate expires, the watchdog sets
the WDR bit in the reset source register and asserts a system reset.
Both writes must occur in the order listed prior to the time-out, but any number of
instructions can be executed between the two writes.
Access this register with 32-bit loads and stores only.
MOTOROLA
C-10
Freescale Semiconductor, Inc.
27
26
25
24
0
0
0
0
11
10
9
8
0
0
0
0
Figure C-12 Watchdog Control Register
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
23
22
21
20
0
0
0
0
7
6
5
4
0
0
0
0
WSTP WDE WDBG WDZE
1000101C
19
18
17
16
0
0
0
0
3
2
1
0
0
0
0
0
MMC2001
REFERENCE MANUAL
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