Table of Contents
Advertisement
COUNT EN — Counter Enable
This bit enables or disables the PWM counter. The counter is actually enabled or dis-
abled some time after the CPU writes this bit, as the enable occurs on the next rising
PCLK edge following internal synchronization. Disabling the counter once it has been
running occurs following the next period match.
0 = PWM disabled. While disabled, the counter is in low-power mode and does
not count. The following events occur:
When the output pin is configured to operate in PWM mode (MODE =1), the
output pin is forced to the setting of the POL bit.
The counter is reset to 00 and frozen.
The contents of the width and period registers are loaded into the compara-
tors.
The comparators are disabled.
If the counter has been running, and the actual disable occurs at the occur-
rence of a period match, an interrupt request may still be generated, even
though the counter is being disabled. To avoid this, write the interrupt enable
control bit (IRQ_EN) to zero when disabling the counter.
1 = PWM is enabled and begins a new period. The following events occur:
The output pin changes state to start a new period (if width != 0 and
period != 0 and width < period).
The counter is released and begins counting
The comparators are enabled
The PWM IRQ bit is set, indicating the start of a new period if IRQ EN is set.
CLK SEL — Clock Select
These bits select the output of the divider chain.
C.6.2 PWM Period Register
The PWM period register (PWMPR) controls the period of the PWM by defining the
number of PCLKs in the period. When the counter value matches the value in this
register, an interrupt is posted and the counter is reset to start another period.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table C-11 Clock Select Field Values
Value
000
001
010
011
100
101
110
111
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
Divide By
4
8
16
64
256
2048
16384
65536
MOTOROLA
C-25
Advertisement
Table of Contents
