Fujitsu FR Series Application Note page 26

Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
BIT[6]: DBEN - Data Buffer Enable
- 0 - Buffering of read data is disabled (default)
- 1 - Buffering of read data is enabled
BIT[5]: PFEN - PreFetch Enable
- 0 - Prefetch of instructions is disabled (default)
- 1 - Prefetch of instructions is enabled
BIT[4]: PFMC - Prefetch Miss Cache enable
- 0 Standard cache algorithm (default)
- 1 Prefetch misses are cached only
BIT[3]: LOCK - Global lock of cache entries
- 0 - Write of cache entries enabled (default)
- 1 - Writing of cache entries is disabled, the cache contents is locked
BIT[2]: ENAB - Instruction cache enable
- 0 - The instruction cache is disabled (default)
- 1 - Enable the instruction cache
BIT[1:0]: SZ[1:0] - Cache size configuration (only valid for MB91V460)
- 00 - 0kByte - Cache disabled
- 01 - 4kByte (1024 entries)
- 10 - 8kByte (2048 entries)
- 11 - 16kByte (4096 entries) (default)
Available settings for FLASHREADT (FMWT):
- B'0000000000000000
||||||||||||||||
||||||||||||||||__ EQ0
|||||||||||||||___ EQ1
||||||||||||||____ EQ2
|||||||||||||_____ EQ3
||||||||||||______ ATD0
|||||||||||_______ ATD1
||||||||||________ ATD2
|||||||||_________ FRAM
||||||||__________ WTC0
|||||||___________ WTC1
||||||____________ WTC2
|||||_____________ WTC3
||||______________ WEXH0 bit
|||_______________ WEXH1 bit
||________________ WTP0
|_________________ WTP1
WTP[1:0]: - Wait cycles for FLASH in page access
WEXH[1:0]: - Minimum WEX High timing requirement
WTC[3:0]: - Wait cycles for FLASH memory access
FRAM: - Wait cycles for F-Bus general purpose RAM memory access
ATD[2:0]: - Duration of the ATDIN signal for FLASH memory access
EQ[3:0]: - Duration of the EQIN signal for FLASH memory access
MCU-AN-300021-E-V10
Start91460.asm
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- 26 - © Fujitsu Microelectronics Europe GmbH