Fujitsu FR Series Application Note page 17

Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
PLLx23 0x0116
PLLx24 0x0117
PLLx25 0x0118
- Main clock 10 MHz (MB91461R only):
Name Setting
PLLSPEED
PLL_10_MHzx2 0x0301
PLL_10_MHzx3 0x0302
PLL_10_MHzx4 0x0303
PLL_10_MHzx5 0x0104
PLL_10_MHzx6 0x0105
PLL_10_MHzx7 0x0106
- Main clock 10 MHz (MB91461R only):
Name Setting
PLLSPEED
PLL_20_MHzx2 0x0301
PLL_20_MHzx3 0x0302
Note: PLLSPEED corresponds to the registers PLLDIVM and PLLDIVN at the addresses
0x48Ch and 0x48Dh.
Note: Never exceed the maximum operation frequency. Check the corresponding data
sheet.
Example:
The PLL should be set to 4 MHz x 16 = 64 MHz.
#set PLLSPEED
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
92 MHz
96 MHz
100 MHz
Resulting Base
Clock
20 MHz
30 MHz
40 MHz
50 MHz
60 MHz
70 MHz
Resulting Base
Clock
40 MHz
60 MHz
0x010F ;<<< 0x48Ch, 0x48Dh: PLLDIVM/N ;
- 17 -
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R,
MB91467D
Remark
Remark
MCU-AN-300021-E-V10
64 MHz